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ASAHI KASEI
[AK2572]
AK2572
APC for Burst Mode Applicable Direct Modulation Laser Diode
FEATURES
Temperature compensation programming function (APC_FF) of Bias current (0~85mA) and Modulation current (0~10mA/0~2.2V) responding to the detected temperature by the On-chip temperature sensor. Stable feedback function in the digital scheme (APC_FB). SFP support TXFAULT function and 1k bit ID field (EEPROM User Area). LD Power leveling function by either Hardware pin control or Register setting. Various alarm functions of Optical output decline (OPTALM), Excessive LD current (CURRALM), Exceptional temperature (TEMPALM) and Irregular external signals (EXTALM1 and EXTALM2). Operation adjustment function via 2-wire Digital interface after assembled into sub-system. On-chip Oscillator allows a Self-running operation. Single 3.3 V [Typ.] power supply.
OUTLINES
The AK2572 enables to keep the optical power of the direct modulation LD (Laser Diode) constant by the APC (Automatic Power Control) circuit. It consists of a current programming function (APC_FF) responding to the temperature characteristics of each LD, and a Digital feedback function (APC_FB) to adjust the LD current based on the monitoring PD (Photo Diode) current. The AK2572 is also applicable to the Burst mode transmission. The device equips a Power leveling function to switch a temperature compensation programming data by either Hardware pin control or Register setting. The On-chip EEPROM (Non-volatile memory) allows to adjust and to keep the individual setting data for each LD characteristics via 2-wire Digital interface after being assembled into sub-system. As 1k bits User Area is allocated in the EEPROM, which supports the ID field of the SFP specification, a proper operation required for the SFP module is realized by using the TXFAULT function.
APPLICATIONS
For LD modules applied to Continuous and Burst mode
ORDERING GUIDE
Product Number AK2572 Package Type QFN28 5.2mmx5.2mm
BLOCK DIAGRAM
AVDD TEMPMON TEMP -SENS PDMON Monitor PD PDIN Cpd Rpd BURST EXTALM2/MOD_CTRL EXTALM1 BIAS RB (12k) *:Open Drain **:Internally Pulled-up PDGAIN ALM Detection TEMPALM CURRALM OPTALM EXTALM2 EXTALM1 OSC 2-wire Digital I/F BIAS MON (x0.012) BIASMON I-DAC2 IOUT2 Ibias ADC
R_TEMP
AVSS
DVDD DVSS
VDDMD
VDDBI VSSBI Imod LDD LD
I-DAC1 EEPROM APC V-DAC3
IOUT1
VOUT3 Vmod
TXFAULT*
BIAS_GEN
SHUTDOW N CONTROL
TXDIS
TEST1 TEST2 TEST3 TEST4
SCL
SDA* W P**

-1-
2004/8
ASAHI KASEI
[AK2572]
Table of Contents
I. PIN DESCRIPTION = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 4 II. ABSOLUTE MAXIMUM RATINGS = = = = = = = = = = = = = = = = = = = = = = = = = = = = 6 III. RECOMMENDED OPERATING CONDITIONS = = = = = = = = = = = = = = = = = = = = = 6 IV. ELECTRICAL CHARACTERISTICS = = = = = = = = = = = = = = = = = = = = = = = = = = = = 6 (1) Current Consumption - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 6 (2) EEPROM Characteristics - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -6 (3) Digital Input / Output Pin DC Characteristics - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -6 (4) Digital Input / Output Pin AC Characteristics - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 7 (5) I-DAC1 Characteristics - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 8 (6) I-DAC2 Characteristics - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 8 (7) V-DAC3 Characteristics - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -8 (8) Current Monitor (BIASMON) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 9 (9) PDGAIN - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -9 (10) DAC_APC - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 9 (11) BIASGEN - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 9 (12) Temperature Sensor - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -9 (13) ADC - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 9 (14) Power On Reset - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 9 (15) On-chip Oscillator - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 9 (16) OPTALM - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -9 V. PACKAGE INFORMATION = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 10 (1) Package Type - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10 (2) Marking Information - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -10 (3) Package Outline Dimension - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10 VI. CIRCUIT DESCRIPTION = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 11 1. 2. 3. 4. Operational Description Notation - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 11 Operation Setting - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 12 I-DAC, V-DAC Functional Part - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -13 APC Functional Part - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -14 4.1 APC_FF Function - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -14 4.2 APC_FB Function - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 15 4.2.1 APC_FB Circuit Block Diagram - - - - - - - - - - - - - - - - - - - - - - - - - - - -16 4.2.2 Normalization of PD Monitoring Current - - - - - - - - - - - - - - - - - - - -16 4.2.3 DAC_APC - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 17 4.2.4 APC_FB Dividing Function - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 17 4.3 APC Operation Setting - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -17 4.4 On-Chip Temperature Sensor (TEMPSENS) Characteristics - - - - - - - - - - - - - 23 4.5 Current Monitor - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -24 Burst Mode Operation - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -25 5.1 Power Leveling [1] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 25 5.2 Power Leveling [2] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 26
5.

-2-
2004/8
ASAHI KASEI
[AK2572]
6.
Alarm Function - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -27 6.1 TEMPALM - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 27 6.2 OPTALM - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -27 6.3 CURRALM - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 27 6.4 EXTALM1, EXTALM2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -27 6.5 TXFAULT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 28 6.5.1 Target Alarm Setting of TXFAULT Output - - - - - - - - - - - - - - - - - -28 6.5.2 Operation at TXFAULT Detection - - - - - - - - - - - - - - - - - - - - - - - - - -28 7. Shutdown Control - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -29 7.1 Shutdown Operation - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 29 7.2 Operation at Shutdown Release - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -29 8. Start-Up Setting in SFP Support Mode - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -30 8.1 TXFAULT Detection at Power-Up and after Release from Shutdown - - - - - - -30 8.1.1 OPTALM - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -30 8.1.2 EXTALM1, EXTALM2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -30 8.2 At Power-On (at TXDIS"L") - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -31 8.3 At Power-On (at TXDIS"H") - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 31 8.4 At TXDIS Detection / Release - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -32 8.5 At TXFAULT Detection / Release - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 33 9. Digital Interface Configuration - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -34 9.1 Memory Configuration - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -34 9.2 Write Protect Operation - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 35 9.3 Read / Write Operation - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -36 9.3.1 Byte Write - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 36 9.3.2 Page Write - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 36 9.3.3 Current Address Read - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -36 9.3.4 Random Read - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -36 9.3.5 Sequential Read - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -37 9.3.6 Data Change - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 37 9.3.7 Start / Stop - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -37 9.4 EEPROM Configuration - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -38 9.5 Register Configuration - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 40 10. Operation Modes - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -44 10.1 Self-Operation Mode - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -44 10.2 Adjustment Mode - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 44 10.3 EEPROM Access Mode - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -44 10.4 Mode Control - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -44 10.5 Operation Mode Change Commands - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 45 10.6 Mode Protection - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 45 11. Example of Adjusting Sequence - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 46
VII. EXTERNAL CIRCUIT EXAMPLE = = = = = = = = = = = = = = = = = = = = = = = = = = = = 47

-3-
2004/8
ASAHI KASEI
[AK2572]
I. PIN DESCRIPTION
Each symbol at I/ O column in the following table means, PWR : PowerVDD or VSS, Ai : Analog input, Ao : Analog output, Di : Digital input, Di_pu : Digital input with pulled-up resistor, Do : Digital output, Do_od : Digital output (Open drain), Dio_od : Digital input/output (Open drain) Pin# Pin Name 1 TEST1 2 TEST2 3 TEST3 4 DVDD 5 DVSS Function Input pin for AKM test. Connect it to DVSS for Normal operation. Input pin for AKM test. Connect it to DVSS for Normal operation. Input pin for AKM test. Connect it to DVSS for Normal operation. Power supply for Digital circuit. Ground for Digital circuit. Alarms such as Optical output decline (OPTALM), Excessive LD current (CURRALM), Exceptional temperature (TEMPALM) and Irregular external signals (EXTALM1 and EXTALM2) can be selected by EEPROM / Register setting as target alarms available on TXFAULT-pin output. When any of the selected alarms (ALM) is detected, TXFAULT-pin TXFAULT becomes "High-Z" output, and it becomes "H" level with a pulled-up resistor connection. This pin is open-drain type and should be connected to DVDD via a 4.7k ~ 10k resistor. With RE_SFP_SET"0" (SFP support mode setting), TXFAULTpin output is held at "H" level when any of the selected alarms is detected till the shutdown request is released by "H" to "L" transition on TXDIS-pin. Serial data input / output pin for Digital interface. This pin is open-drain type and should be connected to DVDD via a SDA 4.7k ~ 10k resistor. I/O Di Di Di PWR PWR Note Connect it to DVSS
6
Connect it Do_od to Pulled-up resistor
7 8 9
10
11 12
13
14 15
Connect it Dio_od to Pulled-up resistor Should not SCL Serial clock input for Digital interface Di be left open Burst signal input. It is active during "H" input period (valid data Should not BURST Di period). When this pin is not used, connect it to DVSS. be left open When this pin is at "H" input, Bias current DAC (I-DAC2) output and Modulation current DAC (I-DAC1 or V-DAC3) output are disabled. Refer to Table 7-1 and Table 7-2. At RE_SFP_SET"0" (SFP support mode setting), a logical sum of Should not TXDIS Di TXFAULT output and TXDIS-pin input become a disable request. be left open At RE_SFP_SET"1", TXDIS-pin input becomes a disable request. When this pin is externally pulled-up, use a higher than 4.7k resistor. When this pin is not used, connect it to DVSS. AVDD Power supply for Analog circuit. PWR AVSS Ground for Analog circuit. PWR Monitoring PD (Photo Diode) voltage input. The detected monitor PD current is I to V converted by external resistor and capacitor. Please adjust the cut-off frequency of an LPF PDIN Ai to be within 5k ~ 10kHz which is composed of external resistor (Rpd) and capacitor (Cpd). When this pin is not used, it is recommended to connect it to AVSS. Bias current monitor. A current multiplied by 0.012 [Typ.] of the I-DAC2 output current is sourced from this pin. When to convert the BIASMON Ao current to a voltage by an external resistor, select the resistor value such that BIASMON-pin voltage1.3 V. VSSBI Ground for I-DAC2. PWR -42004/8

ASAHI KASEI Pin Description (Continued) Pin# Pin Name Function LD Bias current output (Current-sink type : Maximum sink current 85.0 mA [Typ.]). The current value is set by I-DAC2. 16 IOUT2 Please operate the device under IOUT2-pin voltage(VDD1.7 V) condition. When the voltage on this pin becomes lower, a sink current error becomes larger. 17 VSSBI Ground for I-DAC2 18 VDDBI Power supply for I-DAC2. I-DAC1 current output (Current-source type : Maximum sourcing current 10.2 mA [Typ.]). When RE_MODV_SEL"0", this becomes an LD modulation current output and when RE_MODV_SEL"1", it is I to V 19 IOUT1 converted and it can be used as an APD control voltage or a reference voltage for LDD (Laser Diode Driver) etc.. Please operate the device under IOUT1-pin voltage1.3 V. When the voltage on this pin becomes higher, a sourcing current error becomes larger. 20 VDDMD Power supply for I-DAC1. V-DAC3 voltage output pin (Maximum output voltage: 2.2 V [Typ.]). When RE_MODV_SEL"0", this voltage can be used as either an APD control voltage or LDD reference voltage etc.. When 21 VOUT3 RE_MODV_SEL"1", this outputs an LD modulation current control voltage. Please connect an external RC filter (LPF : R1k and C0.01F are recommended) to this pin. PDMON is the Normalized PDIN voltage output pin. Adjust RE_PDGAIN so that PDMON voltage is equal to 1.0 V [typ]. 22 PDMON When APC_FB function or OPTALM function is used, RE_PDGAIN adjustment is required. 23 TEMPMON On-chip temperature sensor voltage output. BIAS resistor connection pin. 24 BIAS Connect this pin to AVSS via a 12k1% resistor. Irregular external signal detect [1] input pin. A polarity of EXTALM1 detection can be selected by RE_EXTALM1_POL. 25 EXTALM1 EXTALM1 can be set as a target TXFAULT output alarm by RE_EXTALM1_SET. When this pin is not used, connect it to DVSS. This pin functions as MOD_CTRL input pin when both RE_SFP_SET"1" and RE_PWR_LVL1_SET"1". This pin becomes EXTALM2 input pin when either RE_SFP_SET "0" or RE_PWR_LVL1_SET"0". When MOD_CTRL-pin function (Power leveling [1] control signal input pin) is selected, Power leveling [1] is executed by a Hardware EXTALM2 / 26 MOD_CTRL pin control. In this case, then, EXTALM2-related function is automatically turned off. When EXTALM2-pin function (Irregular external signal detection [2] input pin) is selected, EXTALM2 is set as a target TXFAULT output alarm by RE_EXTALM2_SET, and RE_EXTALM2_POL sets the polarity of EXTALM2 detection. When this pin is not used, connect it to DVSS. 27 TEST4 Output pin for AKM test. Leave it open for Normal operation. Write protect control pin. This pin is internally pulled-up via a 20k [Typ.] resistor. WP-pin and R_WP_CTRL set the limitation of an 28 WP accessible EEPROM space via Digital interface. Please refer to Section 9.2 for details. -5-
[AK2572]
I/O
Note
Ao
PWR PWR
Ao
PWR Connect it to external RC filter
Ao
Ao Ao Ao Connect it to a resistor Should not be left open
Di
Di
Should not be left open
Do Di_pu
Open
2004/8
ASAHI KASEI
[AK2572]
ABSOLUTE MAXIMUM RATINGS
Item Symbol Power Supply Voltage VDD Ground Level VSS Input Voltage VIN Input Current IIN Storage Temperature Tstg Min. - 0.3 0.0 VSS0.3 - 10 - 55 Max. 6.0 0.0 VDD0.3 10 130 Unit V V V mA Note AVDD, DVDD, VDDMD, VDDBI AVSS, DVSS, VSSBI (Base Voltage) Excluding VDD-pins Excluding VDD-pins
RECOMMENDED OPERATING CONDITIONS
Symbol Min. Typ. Max. Unit Note Ta - 40 + 85 VDD 3.0 3.3 3.5 V 3.3V (-9% / +6%) Power Supply Voltage VSS 0.0 0.0 0.0 V Base Voltage < Important Notice > Please pay attention not to keep the condition of VDD1.5V which makes that the Power On Reset function of AK2572 cannot operate correctly, AK2572 supplies the abnormal LD current and the possibility of damaging LD increases. Item Operating Ambient Temperature
ELECTRICAL CHARACTERISTICS
(1) Current Consumption Item Symbol Min. Typ. Max. Unit Note Current Consumption (All VDD-pins) IDD 21 26 mA [*1], [*2] [*1] It doesn't include the output current of I-DACs. [*2] R_DACxFFh (x1~3), R_DAC1,2_GAIN1, R_DAC3_GAIN0, PDGAIN0dB, PDIN1V (2) EEPROM Characteristics Item Min. Max. Unit Condition EEPROM Write Cycle 1000 times [*] Junction temperature Tj85 EEPROM Data Retention Time 10 year [*] This parameter is characterized and is not 100% tested. < Important Notice > The adjusted data in AKM factory are stored in advance at address location (Device AddressA6h, Address60h) for the offset voltage of the On-chip temperature sensor. If such excessive temperature stress is to be applied to the AK2572 which exceeds a guaranteed EEPROM data retention conditions (for 10 years at 85), it is important to read the pre-determined data in advance and to re-write the same data back into EEPROM after an exposure to the excessive temperature environment. Even if the exposure time is shorter than the retention time, any accelerated temperature stress tests (such as baking) are performed, it is recommended to read the pre-set data first and to re-write it after the test. Access to unused address locations is not functionally guaranteed. Please refer to Section 9.4, "EEPROM Configuration". (3) Digital Input / Output Pin DC Characteristics Item Symbol Min. High Level Input Voltage VIH 2.0 Low Level Input Voltage VIL High Level Output Voltage VOH 0.9VDD Low Level Output Voltage Input Leakage Current Input Leakage Current 2 VOL IL1 IL2 Max. 0.8 0.4 10 350 -6Unit V V V Condition
IOH - 0.2mA IOL1mA (SDA-pin, TXFAULT-pin) V IOL0.2mA (Excluding SDA, TXFAULT) A Excluding WP-pin A WP-pin

2004/8
ASAHI KASEI
[AK2572]
(4) Digital Input / Output Pin AC Characteristics (Serial Interface)
tF tR
SCL
tSU.STA tHD.STA tHD.DAT tSU.DAT tSU.STO
SDA (IN)
tAA tDH tBUF
SDA (OUT)
Parameter Min. Clock Frequency, SCL Clock Pulse Width Low 4.7 Clock Pulse Width High 4.0 Noise Suppression Time Clock Low to Data Out Valid 0.1 Time before a New Transmission 4.7 Start Hold Time 4.0 Start Setup Time 4.7 Data Hold Time 0 Data Setup Time 200 Input Rise Time Input Fall Time Stop Setup Time 4.0 Data Out Hold Time 100 Write Cycle Time [*] This parameter is characterized and is not 100% tested.
Symbol SCL LOW HIGH I AA BUF HD.STA SU.STA HD.DAT SU.DAT R F SU.STO DH WR
Max. 100
100 4.5
1.0 0.3
10
Unit kHz s s ns s s s s s ns s s s ns ms
Note
[*] [*]

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2004/8
ASAHI KASEI
[AK2572]
(5) I-DAC1 Characteristics Item Condition Min. Typ. Max. Unit Note Resolution 8 bit Straight Binary Input CodeFFh Maximum Output IOUT11.3V 9.4 10.2 11.0 mA Current 1 (Source) RE_DAC1_GAIN1 Input CodeFFh Maximum Output IOUT11.3V 0.94 1.02 1.10 mA Current 2 (Source) RE_DAC1_GAIN0 RE_MODV_SEL0 Current Supply at IOUT1VSS A 10 Shutdown TXDIS"H" [*] IOUT11.3V A RE_DAC1_GAIN1 1 LSB Current Step 1 40.0 IOUT11.3V A RE_DAC1_GAIN0 1 LSB Current Step 2 4.0 IOUT11.3V DNL -1 +1 LSB Input Code10h~FFh IOUT11.3V INL -2 +2 LSB Input Code10h~FFh [*] At RE_SFP_SET"0", a logical sum of TXFAULT output and TXDIS-pin input becomes a disable request. Refer to Table 7-1. (6) I-DAC2 Characteristics Item Condition Min. Typ. Max. Unit Note Resolution 8 bit Straight Binary Input CodeFFh Maximum Output IOUT2VDD1.7V 78.2 85.0 91.8 mA Current 1 (Sink) RE_DAC2_GAIN1 Input CodeFFh Maximum Output IOUT2VDD1.7V 39.1 42.5 45.9 mA Current 2 (Sink) RE_DAC2_GAIN0 Current Supply at IOUT2VDD A TXDIS"H" [*] 100 Shutdown A RE_DAC2_GAIN1 1 LSB Current Step 1 IOUT2VDD1.7V 333 A RE_DAC2_GAIN0 1 LSB Current Step 2 IOUT2VDD1.7V 167 IOUT2VDD1.7V DNL -1 +1 LSB Input Code10h~FFh IOUT2VDD1.7V INL -2 +2 LSB Input Code10h~FFh [*] At RE_SFP_SET"0", a logical sum of TXFAULT output and TXDIS-pin input becomes a disable request. Refer to Table 7-1. (7) V-DAC3 Characteristics Item Condition Min. Typ. Max. Unit Note Resolution 8 bit Straight Binary Input CodeFFh Maximum Output 10k (to VSS) 1.11 1.20 1.29 V Voltage 1 RE_DAC3_GAIN1 Input CodeFFh Maximum Output 10k (to VSS) 2.03 2.20 2.37 V Voltage 2 RE_DAC3_GAIN0 Minimum Output 10k (to VDD) Input Code00h 0.2 V Voltage RE_MODV_SEL1 Voltage Supply at 10k (to VDD) 0.2 V Shutdown TXDIS"H" [*] 10k (to VSS) RE_DAC3_GAIN1 1 LSB Voltage Step 1 4.7 mV 10k (to VSS) RE_DAC3_GAIN0 1 LSB Voltage Step 2 8.6 mV 10k (to VSS) DNL -1 +1 LSB Input Code20h~FFh 10k (to VSS) INL -2 +2 LSB Input Code20h~FFh [*] At RE_SFP_SET"0", a logical sum of TXFAULT output and TXDIS-pin input becomes a disable request. Refer to Table 7-1. -8-

2004/8
ASAHI KASEI (8) Current Monitor (BIASMON) Item Condition BIASMON Current Maximum Output Current 1 (Source) Maximum Output Current 2 (Source) (9) PDGAIN Item PDIN Input Range PDGAIN Gain Error BIASMON1.3V BIASMON1.3V BIASMON1.3V 0.94 0.47
[AK2572]
Min.
Typ. 0.012 1.02 0.51
Max.
Unit Time
1.10 0.55
mA mA
Note Based on I-DAC2 Input CodeFFh Input CodeFFh RE_DAC2_GAIN1 Input CodeFFh RE_DAC2_GAIN0 Note
Condition PDMON1V10% PDINPDMON
Min. 0.08 - 0.5
Typ.
Max. 2.5 + 0.5 Typ. 1.195 0.792
Unit V dB Max. 1.255 0.832 +1 Max. Unit V LSB Unit V Unit mV/ V
(10) DAC_APC Item Maximum Output Voltage Minimum Output Voltage DNL (11) BIASGEN Item BIAS-pin Voltage
Condition Test mode, PDMON-pin Test mode, PDMON-pin Test mode, PDMON-pin Condition 12k1%
Min. 1.135 0.752 -1 Min.
Note
Typ. 1.2
Note
(12) Temperature Sensor Item Condition Min. Typ. Max. Voltage Slope TEMPMON-pin Voltage - 12.14 - 11.56 - 10.98 Ta35 Offset Adjustment Target 1.215 [*] This parameter is characterized and is not 100% tested. (13) ADC Item Resolution Maximum Input Voltage Minimum Input Voltage DNL INL (14) Power On Reset Item Detect Voltage (15) On-chip Oscillator Item Clock Frequency (16) OPTALM Item OPTALM Detect Level Condition Min. 2.09 -1 -2 Condition Min. 2.3 Min. Typ. 2.5 Typ. 8.192 Min. 1 / 3.2 1 / 4.3 1 / 6.4 1 / 7.5 Typ. 8 2.20 0 Max. 2.31 +1 +2 Max. 2.7 Max. Unit bit V mV LSB LSB Unit V Unit MHz Max. 1 / 2.8 1 / 3.7 1 / 5.6 1 / 6.5
Note [*]
Note Straight Binary 5%
Note
Condition Test mode
Note
Condition 1/3 setting, PDGAIN0dB 1/4 setting, PDGAIN0dB 1/6 setting, PDGAIN0dB 1/7 setting, PDGAIN0dB
Typ. 1/3 1/4 1/6 1/7
Unit Time Time Time Time
Note

-9-
2004/8
ASAHI KASEI
[AK2572]
PACKAGE INFORMATION
(1) Package Type : 28 pin - QFN
(2) Marking Information : a PIN#1 Indication : b Marking Code : AK2572 c Date Code : YWWX (4 Digit) Y: Year WW : Week (1 ~ 52) X: Manufacturing Identification
AK
(3) Package Outline Dimension
5.20.20 5.00.10 0.600.10
+ -0 0 .1 .2
0.
55
40. C 6
5.20.20 5.00.10 0.220.05 0.210.05
AX M 0 .3
45
45
+0.17 -0.28
0.78
+0.03
0.05

-10-
0.02
-0.02
0.80
0.50 0.05 M
+0.20 -0.10
2004/8
ASAHI KASEI
[AK2572]
CIRCUIT DESCRIPTION
1. Operational Description Notation In order to distinguish various pre-set parameter sources from EEPROM, Registers or Device pins, " Identifier - Main name " notation is used in the AK2572 circuit description as shown in Table 1-1. For ease of operational description, internal signals are sometimes defined which are all expressed in small letters. Table 1-1 Definition of Terms Identifier Register EEPROM Either or Both Register or/and EEPROM BLOCK Internal node R_ E_ RE_ Main name Remark REGISTER name Indicating Register All Capital EEPROM name Indicating EEPROM All Capital REGISTER name Indicating either or both EEPROM name Register or/and EEPROM All Capital BLOCK name All Capital signal name All small letter Example R_DAC2 E_BIAS_TC RE_DAC3_GAIN I-DAC1 vpd
Identification words are assigned to the name of Register / EEPROM as shown in Table 1-2 so that each function can be easily assumed by each name. Table 1-2 Identification Word Classification Classification Suffix Contents Example Identification _SET Functional setting RE_APC_FF_SET suffix _SEL Functional selection E _MODV_SEL _TC Temperature compensation value E_MOD_TC _WIN Window width setting by ALM set RE_TEMP_WIN RE_APC_TRGT _TRGT Target value Functional APC APC related, common for I-DAC1, I-DAC2 and V-DAC3 RE_APC_FF_SET identification DAC I-DAC, V-DAC related E_DAC_SET word BIAS Bias current ( I-DAC2 ) related R_BIAS_FF MOD MOD current ( I-DAC1, V-DAC3 ) related E_MOD_TC EXTRA EXTRA DAC ( DAC not set to MOD ) related R_EXTRA TEMP Temperature sensor related R_TEMP PWR Power leveling function related R_PWR_SEL ALM Alarm related R_TEMPALM_SET FF FeedForward function RE_APC_FF_SET FeedBack function FB RE_APC_FB_SET FB dividing FBRT R_MOD_FBRT TIMER Timer related R_TIMER_OPTALM Gain adjust GAIN E_DAC1_GAIN BURST Burst mode support function related E_BURST_ALM Status signals ST R_TXFLT_ST Signal polarity POL E_EXTALM1_POL < Note > Numeric values in the circuit description of the AK2572 are expressed in Binary, Decimal or Hexadecimal. In order to identify the differences, setting values in Hexadecimal are expressed with a small character "h" suffix.

-11-
2004/8
ASAHI KASEI
[AK2572]
2. Operation Setting The AK2572 can operate following functions as shown in Table 2-1 by EEPROM / Register setting. For further details, please refer to the circuit description at the next page and thereafter. Table 2-1 AK2572 Operation Setting Set-up RE_BURST_SET RE_SFP_SET [*3] RE_PWR_LVL1_SET [*3] RE_PWR_LVL2_SET RE_APC_FF_SET RE_APC_FB_SET RE_OPTALM_SET RE_CURRALM_SET Continuous mode Burst mode SFP_MSA support Shutdown request 0 1 0 0 00 ~ 11 0 ~ 3 00 ~ 11 0 ~ 3 0/1 0/1 x x Logical sum (ORed) TXDIS of TXFAULT and TXDIS x EXTALM2 x *1 *1 *1 *1 0 0 1 11 3 0 0 0 x x TXDIS MOD_CTRL-pin E_MOD_TC1 E_MOD_TC2 1 1 1 0 Related setting
Power leveling [1] EXTALM2 / MOD_CTRL-pin Power leveling [2] APC_FF function APC_FB function OPTALM CURRALM
x EXTALM2 *2 x *2 x *2 x *2
MOD _CTRL x
RE_PWR_SEL E_BIAS_TC0~3 E_MOD_TC0~3
RE_OPTALM RE_TIMER_OPTALM E_CURRALM_BIAS_TC E_CURRALM_MOD_TC
*1 These functions are determined by the corresponding EEPROM / Register setting. Therefore the operations of "" depend on the user's setting. *2 In Burst mode setting (RE_BURST_SET"1", RE_SFP_SET"1"), it is assumed that only APC_FF function is used and no APC_FB function is used (Monitor PD, CURRALM and OPTALM are not used). [*3] Setting of RE_SFP_SET"0" and R_PWR_LVL1_SET"1" is prohibited.

-12-
2004/8
ASAHI KASEI 3. I-DAC, V-DAC Functional Part
[AK2572]
The AK2572 equips Current source type I-DAC1 (Max. sourcing current10.2 mA [Typ.]) and Voltage output type V-DAC3 (Max. output voltage2.2 V [Typ.]) for the LD modulation current setting, and Current sink type I-DAC2 (Max. sink current85.0 mA [Typ.] ) for the bias current setting. Selection of enable / disable each DAC is set by RE_DAC_SET. Output current of I-DAC1 (Max. value10.2 mA / 1.02 mA [Typ.]) and I-DAC2 (Max. value85.0 mA / 42.5 mA [Typ.]), and output voltage of V-DAC3 (Max. value2.2 V / 1.2 V [Typ.]) can be switched by gain setting. This gain switching allows to lower current consumption and to improve the accuracy per 1 LSB. In Tables 3-1 ~ 3-3, the characteristics of I-DAC2, I-DAC1 and V-DAC3 are shown. I-DAC2 directly sets the LD bias current. A current multiplied by a factor of 0.012 [Typ.] of I-DAC2 set value is output (Current source) on BIASMON-pin. Table 3-1 I-DAC2 characteristics (I-DAC2 is set "Enabled" / "Disabled" by RE_DAC_SET [1]"1" / "0") Max. output current (CodeFFh)Typ Range Typ Current/step Typ RE_DAC2_GAIN Gain 333 A 1 1 85.0 mA 0 ~ 85.0 mA 167 A 0 1/2 42.5 mA 0 ~ 42.5 mA [Note] I-DAC2 characteristics : Resolution8 bits, DNL1 LSB (DAC code10h ~ FFh) Output current variation at Maximum DAC code (FFh)Typ.8 % Temperature compensation data (Retained in EEPROM), which are set for I-DAC1 and V-DAC3, can be selected by RE_MODV_SEL setting as shown in Table 3-4. When E_MOD_TC (128 address locations) is assigned as the setting data, I-DAC1(RE_MODV_SEL"0") generates a reference current of the modulation current to external Laser Diode Driver (LDD), and V-DAC3 (RE_MODV_SEL"1") generates a reference voltage of the Modulation current to external LDD. A voltage driver type LDD can also be adopted by converting an I-DAC1 output current to a voltage by external resistors or by using V-DAC3 output voltage. When E_EXTRA_TC (32 address locations) is assigned as the setting data, I-DAC1 output (RE_MODV_SEL"1") or V-DAC3 output (RE_MODV_SEL"0") can be used as APD control voltage or LDD reference voltage etc.. When temperature compensation by E_EXTRA_TC is not required, same data should be written at all address locations. Table 3-2 I-DAC1 characteristics (I-DAC1 is set "Enabled" / "Disabled" by RE_DAC_SET [0]"1" / "0") RE_DAC1_GAIN Gain Max. output current (CodeFFh)Typ Range Typ Current / stepTyp 40 A 1 1 10 .2 mA 0 ~ 10 .2 mA 4 A 0 1/10 1.02 mA 0 ~ 1.02 mA [Note] I-DAC1 characteristics : Resolution8 bits, DNL1 LSB (DAC code10h ~ FFh) Output current variation at Maximum DAC code (FFh)Typ.8 % Table 3-3 V-DAC3 characteristics (V-DAC3 is set "Enabled" / "Disabled" by RE_DAC_SET [2]"1" / "0") RE_DAC3_GAIN Gain Max. output voltage (CodeFFh)Typ Range Typ Voltage / stepTyp 1 1.2 / 2.2 1.2 V 0 ~ 1.2 V 4.7 mV 0 1 2.2 V 0 ~ 2.2 V 8.6 mV [Note] V-DAC3characteristics : Resolution8 bits, DNL1 LSB (DAC code20h ~ FFh) Output voltage variation at Maximum DAC code (FFh)Typ.8 % Table 3-4 RE_MODV_SEL setting RE_MODV_SEL I-DAC1 V-DAC3 0 E_MOD_TC E_EXTRA_TC 1 E_EXTRA_TC E_MOD_TC [Note] Although E_MOD_TC has 128 address locations and E_EXTRA_TC has 32 address locations, temperature resolution of each temperature compensation data is 0.75 [typ.] because of the temperature compensation data is derived from a linear interpolation method (Refer to Section 4.1).

-13-
2004/8
ASAHI KASEI
[AK2572]
4. APC Functional Part Circuit configuration of the APC part is shown in Figure 4-1. The AK2572 is formed with APC_FF function which sets the programmed current with corresponding to the detected temperature by On-chip temperature sensor and APC_FB function which controls with feedback function to keep the monitoring photo diode current constant. By properly combining APC_FF and APC_FB functions together by EEPROM / Register setting, a proper LD Bias current / Modulation current can be generated. Figure 4-1 APC Circuit Block Diagram
TEMPALM threshold (E_TEMPALM) V-DAC3 operation setting (RE_DAC_SET[2]) V-DAC3 gain setting (RE_DAC3_GAIN) I-DAC1,V-DAC3 data selection (RE_MODV_SEL) R_DAC3
TEMPMON
On-chip temperature sensor offset adjusting (RE_TEMP_OFFSET) Temp. sensor (TEMPSENS)
TEMP ALM
Tempalm
V-DAC3 VOUT3
EXTRA_DAC value (R_EXTRA) ADC (Time sharing) Temperature equivalent value (R_TEMP) EEPROM MOD: APC_FF value (R_MOD_FF) MOD: APC_FB dividing (RE_MOD_FBRT) K_MOD _FBRT + MOD data I-DAC1 operation setting (RE_DAC_SET[0]) I-DAC1 gain setting (RE_DAC1_GAIN) IMOD I-DAC1 IOUT1
Burst mode setting (RE_BURST_SET) BURST_ CONTROL
BURST
B_ EXTALM polarity setting (RE_EXTALM1_POL) (RE_EXTALM2_POL)
APC_FF setting (RE_APC_FF_SET) APC_FB initial value setting (RE_APC_INIT_SET) Power Leveling[1] setting (RE_PWR_LVL1_SET) (RE_SFP_SET) Extalm1 Extalm2 Power Leveling[2] setting (RE_PWR_LVL2_SET) (RE_PWR_SEL)
R_DAC1
EXTALM1 Pin setting (RE_SFP_SET (RE_PWR_LVL1_SET EXTALM2 /MOD_CTRL PDMON PDGAIN setting (RE_PDGAIN) PDIN PDGAIN Cpd Rpd
EXTALM
BIAS: APC_FB dividing APC_FB setting I-DAC2 operation setting (RE_APC_FB_SET) (RE_BIAS_FBRT) (RE_DAC_SET[1]) I-DAC2 gain setting K_BIAS (RE_DAC2_GAIN) _FBRT BIAS: APC_FF value (R_BIAS_FF) APC_FB value (R_APC_FB) Over current threshold (RE_CURRALM_MOD) (RE_CURRALM_BIAS) R_DAC1/R_DAC3 R_DAC2 OPTALM _COMP Optalm + BIAS data (R_DAC2) I-DAC2
IBIAS IOUT2 BIASMON x 0.012
Mod_Ctrl Digital Filter APC_ COMP 1/N 1/s
Monitor PD
CURRALM
Curralm
vpd
OPALM threshold (RE_OPTALM)
APC target (RE_APC_TRGT)
DAC_APC
vapc_ref
ATT
optalm_ref
4. 1 APC_FF Function APC_FF functional block diagram is shown in Figure 4-2. Output voltage of On-chip temperature sensor, which responds to the detected temperature, is A-to-D converted (8 bits) in every temperature detection cycle (64 msec [Typ.]). The resulting data (R_TEMP) is used as an EEPROM address and the data (8 bits) retained in EEPROM at that address location is read out. The read out data is set to DAC and by supplying a proper current to LD in response to temperature characteristics of each LD, APC_FF function is realized as in the procedure above. Namely, the EEPROM address corresponds to temperature and the data corresponds to the bias current and the modulation current at that temperature. Although allocated EEPROM space for APC_FF is 7 bits (128 address locations), it is extended to 8 bits equivalent data (256 address locations) by utilizing a linear interpolation of the current programming data as shown in the following equation. < Linear interpolation of E_BIAS_TC and E_MOD_TC > Given that the detected temperature data are R_TEMP7:0z2x, 2x+1, R_TEMP7:1x, and the temperature compensated data retained in EEPROM are E_BIAS_TC(x), E_MOD_TC(x), and the data derived from linear interpolation are R_BIAS_FF(z), R_MOD_FF(z) respectively, R_BIAS_FF(z)E_BIAS_TC(x1)E_BIAS_TC(x)E_BIAS_TC(x1)xR_TEMP0/ 2 R_MOD_FF(z)E_MOD_TC(x1)E_MOD_TC(x)E_ MOD _TC(x1)xR_TEMP0/ 2 But at x0 (R_TEMP7:0z0, 1), E_BIAS_TC(x)E_BIAS_TC(x1)E_BIAS_TC(0) E_MOD_TC(x)E_MOD_TC(x1)E_MOD_TC(0) -142004/8
ASAHI KASEI
[AK2572]
< Linear interpolation of E_EXTRA_TC > Given that the detected temperature data are R_TEMP7:0z8y, 8y+1, , 8y+7, R_TEMP7:3y, and the temperature compensated data retained in EEPROM is E_EXTRA_TC(y), and data calculated by linear interpolation is R_EXTRA(z) (DAC loading E_EXTRA_TC data is selected by RE_MODV_SEL ), R_EXTRA(z)E_EXTRA_TC(y1)E_EXTRA_TC(y)E_EXTRA_TC(y1)xR_TEMP2:0/ 8 But at y0 (R_TEMP7:0z0 ~ 7), E_EXTRA_TC(y)E_EXTRA_TC(y1)E_EXTRA_TC(0) In order to keep the optical power of LD constant by APC_FF method, regardless of environmental temperature changes, it is necessary to write and store the data of Bias current and Modulation current at each in the temperature-corresponding EEPROM address when to adjust each LD module. In normal operation, On-chip oscillator for temperature compensation of the current to drive LD modules automatically executes the temperature detection and the current setting. Those temperature compensated data for Bias current, Modulation current and EXTRA_DAC which are all derived from the linear interpolation, have approximately 0.75 resolution and can automatically adjust LD current and reference voltage for external circuit in approximately 0.75 step. The On-chip temperature sensor is designed to cover the temperature range from - 40 ~ +115 under the ADC operating voltage range (0 ~ 2.2 V [Typ.]). As to the relation between temperature sensor and ADC code, please refer to Section "4.4 On-chip Temperature Sensor Characteristics". Figure 4-2 APC_FF Functional Block Diagram
Output voltage from TEMPSENS is A-to-D converted On-chip Temperature Sensor (TEMPSENS) ADC (8bit) ADC output R_TEMP[7:0] R_BIAS_FF I-DAC2 Digital code changes in response to temperature change Temperature t [] Memory for Imod (I-DAC1 or V-DAC3) 128 address Memory for Ibias (I-DAC2) 128 address A proper current value data should be written in advance at each address location which corresponds to each temperature value R_MOD_FF, R_BIAS_FF (Linear interpolation of APC_FF data): R(z) = E(x-1) + {E(x)-E(x-1)} * R_TEMP[0] 2 Ibias Address Data Read out the data in EEPROM with referring Digital code as EEPROM address Set the read out data into I-DAC1(V-DAC3) and I-DAC2, then control LD current R_MOD_FF EEPROM I-DAC1 (V-DAC3) LDD Imod LD
R_TEMP[7:1]
TEMPSENS output Voltage V [V] Output voltage proportionally changes in response to temperature change Temperature t []
E(x): E_BIAS_TC or E_MOD_TC at x=R_TEMP[7:1] R(z): R_BIAS_FF or R_MOD_FF at z=R_TEMP[7:0]=2x, 2x+1
4.2 APC_FB Function APC_FB functional block diagram is shown in Figure 4-3. In APC_FB block, an amplified PDIN voltage by gain value (vpd) and DAC_APC output voltage (vapc_ref) are compared at APC_COMP, and the feedback current (R_APC_FB) is calculated at digital filter so that vpd and vapc_ref are equal. The cut-off frequency (fpd), which is fixed by Rpd and Cpd, should be set as follows: 5 kHzfpd10 kHz

-15-
2004/8
ASAHI KASEI Figure 4-3 APC_FB Functional Block Diagram
APC_FF TEMPSENS ADC R_TEMP + EEPROM APC_FB Initial value setting is possible in response to temperature at the start-up PDMON Monitor PD 512kHz [Typ.] PDIN PDGAIN Rpd Cpd Dispersion of monitor PD current is cancelled and a normalized voltage is output on PDMON-pin RE_APC_TRGT DAC_APC vpd APC_ COMP comp_out 1/N 1/s A proper APC_FB initial value setting can shorten the start-up time DIGITAL FILTER R_APC_FB R_APC_FBIV
[AK2572]
DAC R_DAC2 R_DAC1/R_DAC3
DAC code is incremented or decremented by 1 LSB step in order to prevent the excessive current vapc_ref
4.2.1 APC_FB Circuit Block Diagram The operation of each block is shown in Table 4-1. Table 4-1 APC_FB Block Diagram Descriptions Block Function Note Amplified PDIN voltage by gain value (vpd) and APC target value (vapc_ref) are APC_ compared and if "vpdvapc_ref", UP (increment) request or if "vpdvapc_ref", DOWN COMP (decrement) request is output on digital filter. The comparison is made at 512 kHz [Typ.]. DIGITAL From the APC_COMP result, R_APC_FB value is calculated so that vpd and vapc_ref FILTER are equal. Amplified PDIN voltage by gain value is output on PDMON-pin. Input range is 0.08 V ~ PDGAIN 2.5V. Adjust the gain so that PDMON output voltage is equal to 1.0V [Typ.]. When to set a normalized voltage lower than 1.0 V, adjust it by utilizing external resistor-divider etc.. APC reference voltage (vapc_ref) is output. Output voltage is adjustable by DAC_APC RE_APC_TRGT setting. APC_FB operates such that the amplified PDIN voltage by gain value equals to DAC_APC output. 4.2.2 Normalization of PD Monitoring Current A monitor PD current is converted into average voltage by an external resistor and a capacitor and it is fed on PDIN-pin. Input voltage range of PDIN at initial adjustment is listed in Table 4-2. PDIN voltage is amplified by gain value at PDGAIN block and it is output on PDMON-pin. Adjust PDGAIN so that output voltage on PDMON-pin is 1.0 V [Typ.]. In Table 4-3, adjustable range of RE_PDGAIN is listed. When a lower than 1.0 V [Typ.] is required as a normalized voltage, voltage-divide it by an external resistor-divider etc.. Table 4-2 PDIN Input Condition Item Min. PDIN input voltage 0.08V Table 4-3 PDGAIN Setting RE_PDGAIN 00 0000 (00h) 00 0001 (01h) 11 1110 (3Eh) 11 1111 (3Fh) Max. 2.5V Note
Set-up gain Typ. 23.5 dB 23.0 dB - 7.5 dB - 8.0 dB -16-
Note
0.5 dB / step

2004/8
ASAHI KASEI 4.2.3 DAC_APC DAC_APC outputs APC_FB reference voltage (vapc_ref). vapc_ref is adjusted by RE_APC_TRGT. The relation of RE_APC_TRGT and vapc_ref is shown in Table 4-4. Table 4-4 DAC_APC Setting DAC_APC output : vapc_ref Typ. R_APC_TRGT 0 0000 (00h) 0.792 V 0 1111 (0Fh) 0.987 V 1 0000 (10h) 1.000 V 1 0001 (11h) 1.013 V 1 1111 (1Fh) 1.195 V Note
[AK2572]
13mV / step
4.2.4 APC_FB Dividing Function The AK2572 has a function to divide the R_APC_FB value into both Bias current and Modulation current, which is calculated by APC_FB function. By utilizing this function, the extinction ratio can be kept constant by applying feedback operation on Bias and Modulation currents. Block diagram in Figure 4-4 and the coefficient factor used for dividing calculation in Table 4-5 are shown. Figure 4-4 APC Feedback Dividing Block Diagram
RE_MOD_FBRT R_APC_FB R_MOD_FB RE_DAC1_GAIN (RE_DAC3_GAIN) Imod (Vmod)
K_MOD _FBRT
I-DAC1 (V-DAC3)
K_BIAS _FBRT
R_BIAS_FB
I-DAC2
Ibias
RE_BIAS_FBRT
RE_DAC2_GAIN
Table 4-5 K_BIAS_FBRT, K_MOD_FBRT RE_APC_FB_SET K_BIAS_FBRT 00 (0) 0 01 (1) 0 10 (2) 1
Note Without Feed Back (FB) FB on Modulation current control only FB on Bias current control only FB ratio is divided for both Bias and 11 3 R_MOD_FBRT/128 R_BIAS_FBRT/128 Modulation currents [*] [*] R_BIAS_FBRT127, R_MOD_FBRT127 (Be noted that full range of APC_FB current from I-DACs is limited since the dividing coefficients are mutually multiplied)
K_MOD_FBRT 0 1 0
4.3 APC Operation Setting Combination of APC function is set by RE_APC_FF_SET and RE_APC_FB_SET. Setting examples are shown in Table 4-6 and Figures 4-5 ~ 4-13. Handling of the data, which are retained in the temperature compensated Bias data space (E_BIAS_TC) and the temperature compensated Modulation data space (E_MOD_TC), is automatically altered by APC setting. Relation between APC setting and the data retained in EEPROM space is listed in Table 4-7. As to the memory space of E_BIAS_TC and E_MOD_TC, please refer to Table 9-3. Lists of the data for each APC combination are shown in Table 4-8 and 4-9. RE_APC_FF_SET is configured with 2 bits and it selects the I-DAC for FF (Feed Forward) setting. RE_APC_FB_SET is configured with 2 bits and it selects the I-DAC for FB (FeedBack) setting. The upper bit shows the BIAS side and the lower bit shows the MOD (Modulation) side.

-17-
2004/8
ASAHI KASEI Table 4-6 APC Operation Setting Examples RE_APC RE_APC BIAS MOD _FF_SET _FB_SET Current Current
[AK2572]
Note
Figure
Set MOD (Modulation) for FF (Feed Forward) setting. Degraded LD characteristic is compensated by BIAS 01 10 FB FF only. Initial value of BIAS FB (FeedBack) can be 4-5 (1) (2) programmed in response to a start-up temperature (Set by RE_APC_INIT_SET). Set BIAS for FF setting. 10 01 Degraded LD is compensated by MOD only. Initial FF FB 4-6 (2) (1) value of MOD FB can be programmed in response to a start-up temperature (Set by RE_APC_INIT_SET). 11 00 Set both BIAS and MOD for FF setting. No FF FF 4-7 (3) (0) compensation of degraded LD is made. 11 01 Set both BIAS and MOD for FF setting. FF FF+FB 4-8 (3) (1) Compensation of degraded LD is made by the MOD. 11 10 Set both BIAS and MOD for FF setting. FF+FB FF 4-9 (3) (2) Compensation of degraded LD is made by BIAS. Compensation of degraded LD is made in accordance 00 11 with the dividing coefficient for BIAS and MOD initial FB FB 4-10 (0) (3) value of FB can be programmed in response to a start-up temperature (Set by RE_APC_INIT_SET). MOD outputs a current that is sum of the divided FB current and the FF setting current. 01 11 BIAS outputs a current that is proportional to the FB FF+FB 4-11 (1) (3) divided FB current. Initial value of BIAS FB can be programmed in response to a start-up temperature (Set be RE_APC_INIT_SET). BIAS outputs a current that is sum of the divided FB current and the FF setting current. 10 11 FB FF+FB MOD outputs a current that is proportional to the 4-12 (2) (3) divided FB current. APC_FB initial value setting is prohibited in this setting [*]. Both in BIAS and MOD, a current that is 11 11 proportional to the divided FB is added to the FF FF+FB FF+FB 4-13 (3) (3) setting current and compensation of degraded LD is made by the FB current. [*] RE_APC_INIT_SET"1" setting is prohibited when RE_APC_FF_SET"10 (2)" and RE_APC_FB_SET "11 (3)" (BIASFFFB / MODFB) Fig.4-5 Setting Example 1 (BIASFB,MODFF)
R_MOD_FF R_APC_FB 0 R_MOD_FB =0 R_MOD RE_DAC1_GAIN (RE_DAC3_GAIN) I-DAC1(V-DAC3) 10/255 (2.2/255) I-DAC2 R_BIAS 85/255 G_DAC2 Ibias 0 G_DAC1 (G_DAC3) Imod (Vmod)
Fig.4-6 Setting Example 2 (BIASFF,MODFB)
R_MOD_FF=0 R_APC_FB 1 R_MOD_FB =R_APC_FB R_MOD RE_DAC1_GAIN (RE_DAC3_GAIN) I-DAC1(V-DAC3) 10/255 (2.2/255) I-DAC2 R_BIAS 85/255 G_DAC2 Ibias G_DAC1 (G_DAC3) Imod (Vmod)
R_BIAS_FB =R_APC_FB 1
R_BIAS_FB =0
R_BIAS_FF=0 R_MOD=R_MOD_FF R_BIAS=R_BIAS_FB=R_APC_FB
RE_DAC2_GAIN G_DAC1= 1 or 0.1 G_DAC2= 1 or 0.5 G_DAC3= 1 or 1.2/2.2
R_BIAS_FF R_MOD=R_MOD_FB=R_APC_FB R_BIAS=R_BIAS_FF
RE_DAC2_GAIN G_DAC1= 1 or 0.1 G_DAC2= 1 or 0.5 G_DAC3= 1 or 1.2/2.2

-18-
2004/8
ASAHI KASEI Fig.4-7 Setting Example 3 (BIASFF,MODFF)
R_MOD_FF R_APC_FB 0 R_MOD_FB =0 R_MOD RE_DAC1_GAIN (RE_DAC3_GAIN) I-DAC1(V-DAC3) 10/255 (2.2/255) I-DAC2 R_BIAS 85/255 G_DAC2 Ibias 0 G_DAC1 (G_DAC3) Imod (Vmod)
[AK2572] Fig.4-8 Setting Example 4 (BIASFF,MODFF+FB)
R_MOD_FF R_APC_FB 1 R_MOD_FB =R_APC_FB R_MOD RE_DAC1_GAIN (RE_DAC3_GAIN) I-DAC1(V-DAC3) 10/255 (2.2/255) I-DAC2 R_BIAS 85/255 G_DAC2 Ibias G_DAC1 (G_DAC3) Imod (Vmod)
R_BIAS_FB =0 0
R_BIAS_FB =0
R_BIAS_FF R_MOD=R_MOD_FF R_BIAS=R_BIAS_FF
RE_DAC2_GAIN G_DAC1= 1 or 0.1 G_DAC2= 1 or 0.5 G_DAC3= 1 or 1.2/2.2
R_BIAS_FF R_MOD=R_MOD_FF+R_MOD_FB =R_MOD_FF+R_APC_FB R_BIAS=R_BIAS_FF
RE_DAC2_GAIN G_DAC1= 1 or 0.1 G_DAC2= 1 or 0.5 G_DAC3= 1 or 1.2/2.2
Fig.4-9 Setting Example 5 (BIASFF+FB,MODFF) Fig.4-10 Setting Example 6 (BIASFB,MODFB)
R_MOD_FF R_APC_FB 0 R_MOD_FB =0 R_MOD RE_DAC1_GAIN (RE_DAC3_GAIN) I-DAC1(V-DAC3) 10/255 (2.2/255) I-DAC2 R_BIAS 85/255 G_DAC2 Ibias K_BIAS _FBRT G_DAC1 (G_DAC3) Imod (Vmod) R_APC_FB RE_MOD_FBRT R_MOD_FF=0 R_MOD_FB R_MOD RE_DAC1_GAIN (RE_DAC3_GAIN) I-DAC1(V-DAC3) K_MOD _FBRT 10/255 (2.2/255) I-DAC2 R_BIAS_FB R_BIAS 85/255 G_DAC2 Ibias G_DAC1 (G_DAC3) Imod (Vmod)
R_BIAS_FB =R_APC_FB 1
R_MOD=R_MOD_FF
R_BIAS_FF
RE_BIAS_FBRT RE_DAC2_GAIN G_DAC1= 1 or 0.1 G_DAC2= 1 or 0.5 G_DAC3= 1 or 1.2/2.2
R_BIAS_FF=0
RE_DAC2_GAIN G_DAC1= 1 or 0.1 G_DAC2= 1 or 0.5 G_DAC3= 1 or 1.2/2.2
R_BIAS=R_BIAS_FF+R_BIAS_FB =R_BIAS_FF+R_APC_FB
R_MOD=R_MOD_FB R_MOD_FB=K_MOD_FBRT*R_APC_FB R_BIAS=R_BIAS_FB R_BIAS_FB=K_BIAS_FBRT*R_APC_FB
Fig.4-11 Setting Example 7 (BIASFB,MODFF+FB) Fig. 4-12 Setting Example 8 (BIASFF+FB,MODFB)
RE_MOD_FBRT R_APC_FB R_MOD_FF R_MOD_FB R_MOD RE_DAC1_GAIN (RE_DAC3_GAIN) I-DAC1(V-DAC3) K_MOD _FBRT 10/255 (2.2/255) I-DAC2 K_BIAS _FBRT R_BIAS_FB R_BIAS 85/255 G_DAC2 Ibias K_BIAS _FBRT R_BIAS_FB R_BIAS 85/255 G_DAC2 G_DAC1 (G_DAC3) Imod (Vmod) RE_MOD_FBRT R_APC_FB R_MOD_FF=0 R_MOD_FB R_MOD RE_DAC1_GAIN (RE_DAC3_GAIN) I-DAC1(V-DAC3) K_MOD _FBRT 10/255 (2.2/255) I-DAC2 Ibias G_DAC1 (G_DAC3) Imod (Vmod)
RE_BIAS_FBRT
R_BIAS_FF=0
RE_DAC2_GAIN G_DAC1= 1 or 0.1 G_DAC2= 1 or 0.5 G_DAC3= 1 or 1.2/2.2
RE_BIAS_FBRT
R_BIAS_FF
RE_DAC2_GAIN G_DAC1= 1 or 0.1 G_DAC2= 1 or 0.5 G_DAC3= 1 or 1.2/2.2
R_MOD=R_MOD_FF+R_MOD_FB R_MOD_FB=K_MOD_FBRT*R_APC_FB R_BIAS=R_BIAS_FB R_BIAS_FB=K_BIAS_FBRT*R_APC_FB
R_MOD=R_MOD_FB R_MOD_FB=K_MOD_FBRT*R_APC_FB R_BIAS=R_BIAS_FF+R_BIAS_FB R_BIAS_FB=K_BIAS_FBRT*R_APC_FB
Fig.4-13 Setting Example 9 (BIASFF+FB, MODFF+FB)
RE_MOD_FBRT R_APC_FB R_MOD_FF R_MOD_FB R_MOD RE_DAC1_GAIN (RE_DAC3_GAIN) I-DAC1(V-DAC3) K_MOD _FBRT 10/255 (2.2/255) I-DAC2 K_BIAS _FBRT R_BIAS_FB R_BIAS 85/255 G_DAC2 Ibias G_DAC1 (G_DAC3) Imod (Vmod)
RE_BIAS_FBRT
R_BIAS_FF
RE_DAC2_GAIN G_DAC1= 1 or 0.1 G_DAC2= 1 or 0.5 G_DAC3= 1 or 1.2/2.2
R_MOD=R_MOD_FF+R_MOD_FB R_MOD_FB=K_MOD_FBRT*R_APC_FB R_BIAS=R_BIAS_FF+R_BIAS_FB R_BIAS_FB=K_BIAS_FBRT*R_APC_FB

-19-
2004/8
ASAHI KASEI
[AK2572]
Table 4-7 Relation of APC Operation Setting and Register Retaining Temperature Compensation Data E_BIAS_TC [*1] E_MOD_TC [*1][*2] RE_APC_ RE_APC_ RE_APC_ (Temperature compensation (Temperature compensation FF_SET FB_SET INIT_SET Data for I-DAC2) Data for I-DAC1or V-DAC3) 00 (0) x 0 01 (1) 1 R_APC_FBIV 00 (0) 0 10 (2) 1 R_APC_FBIV 0 11 (3) 1 R_APC_FBIV 00 (0) x R_MOD_FF 0 R_MOD_FF 01 (1) 1 Prohibited 01 (1) 0 R_MOD_FF 10 (2) 1 R_APC_FBIV R_MOD_FF 0 R_MOD_FF 11 (3) 1 R_APC_FBIV R_MOD_FF 00 (0) x R_BIAS_FF 0 R_BIAS_FF 01 (1) 1 R_BIAS_FF R_APC_FBIV 10 (2) 0 R_BIAS_FF 10 (2) 1 Prohibited 0 R_BIAS_FF 11 (3) 1 Prohibited 11 (3) xx x R_BIAS_FF R_MOD_FF *1 As to the EEPROM memory space of E_BIAS_TC, E_MOD_TC, refer to Table 9-3. *2 By RE_MODV_SEL setting, DAC (either I-DAC1 or V-DAC3) loading the temperature compensation data retained in E_MOD_TC is selected. Refer to Table 3-4. *3 Register content Register Content Note R_BIAS_FF Bias current data (APC_FF) Set to I-DAC2 R_MOD_FF Modulation current data (APC_FF) Set to either I-DAC1 or V-DAC3. Added to the APC_FF value after R_APC_FBIV APC_FB initial data. dividing calculation.

-20-
2004/8
ASAHI KASEI Table 4-8 Operation Setting and APC Operation at Self-Operation Mode
RE_APC_ RE_APC RE_APC_ R_BIAS_FF FB_SET _FF_SET INIT_SET 00 (0) 00 (0) 01 (1) 10 (2) 11 (3) 00 (0) 01 (1) 10 (2) 11 (3) 00 (0) 01 (1) 10 (2) 11 (3) 11 (3) 00 (0) x x x x 0 1 0 1 [*] 0 1 x 0 1 0 1 0 1 [*] x 0 1 01 (1) 0 1 10 (2) 0 1 [*] 11 (3) x R_MOD_FF R_APC _FB 0 0 0 0 FB FB FB FB FB FB FB FB FB FB FB FB FB FB FB FB FB FB R_APC _FBIV 0 0 0 0 0 E_MOD_TC 0 0 E_MOD_TC 0 0 E_BIAS_TC 0 E_BIAS_TC 0 0 0 E_BIAS_TC 0 E_BIAS_TC 0 0 R_BIAS _FBRT E_BIAS _FBRT E_BIAS _FBRT E_BIAS _FBRT E_BIAS _FBRT E_BIAS _FBRT E_BIAS _FBRT R_MOD _FBRT E_MOD _FBRT E_MOD _FBRT E_MOD _FBRT E_MOD _FBRT E_MOD _FBRT E_MOD _FBRT K_BIAS _FBRT 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 R_BIAS _FBRT/128 R_BIAS _FBRT/128 R_BIAS _FBRT/128 R_BIAS _FBRT/128 R_BIAS _FBRT/128 R_BIAS _FBRT/128 K_MOD _FBRT 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 R_MOD _FBRT/128 R_MOD _FBRT/128 R_MOD _FBRT/128 R_MOD _FBRT/128 R_MOD _FBRT/128 R_MOD _FBRT/128 MOD BIAS (R_DAC1 (R_DAC2) or R_DAC3) 0 0 0 FF FF 0 FF FF 0 0 0 FF FF FF FB FB FB FB FF + FB FF + FB FB FB FB FB FF + FB FF + FB FB FB FF + FB FB FB FF + FB 0 0 FF FF 0 FF FB FB FF + FB FF + FB FB FF + FB
[AK2572]
E_BIAS E_MOD _TC _TC FF FF FF FF
0 0 0 E_MOD_TC E_BIAS_TC 0 E_BIAS_TC E_MOD_TC 0 0 0 E_BIAS_TC E_BIAS_TC E_BIAS_TC 0 0 0 0 E_BIAS_TC E_BIAS_TC 0 0 0 0 E_BIAS_TC 0 0 E_MOD_TC 0 0 E_MOD_TC 0 0 E_MOD_TC E_MOD_TC 0 E_MOD_TC 0 0 E_MOD_TC E_MOD_TC 0
01 (1)
10 (2)
FB_INIT FF FF FF FB_INIT FF FF FB_INIT FF FF FB_INIT FF FF FF FB_INIT FB_INIT FF FF FF FF FF
E_BIAS_TC E_MOD_TC
[*] It is prohibited to set , or . < MS0290-E-01> -212004/8
ASAHI KASEI Table 4-9 Operation Setting and APC Operation at Adjustment Mode
RE_APC _FB_SET 00 (0) 01 (1) 10 (2) RE_APC _FF_SET xx xx xx 00 (0) RE_APC_ INIT_SET x x x 0 1 01 (1) 11 (3) 10 (2) 0 1 0 1 11 (3) 0 1 R_ BIAS _FF R_MOD_FF R_APC_FB I/F I/F I/F 0 [*2] 0 [*2] 0 [*2] 0 [*2] I/F I/F I/F I/F I/F I/F I/F 0 [*2] 0 [*2] I/F I/F 0 [*2] 0 [*2] I/F I/F 0 FB FB FB FB FB FB FB FB FB FB R_APC _FBIV 0 [*2] I/F I/F 0 [*2] I/F 0 [*2] I/F 0 [*2] I/F 0 [*2] I/F R_BIAS_ FBRT I/F [*1] I/F [*1] I/F [*1] I/F I/F I/F I/F I/F I/F I/F I/F R MOD _ FBRT I/F [*1] I/F [*1] I/F [*1] I/F I/F I/F I/F I/F I/F I/F I/F K_ BIAS _FBRT 0 0 1 R_BIAS_FBRT /128 R_BIAS_FBRT /128 R_BIAS_FBRT /128 R_BIAS_FBRT /128 R_BIAS_FBRT /128 R_BIAS_FBRT /128 R_BIAS_FBRT /128 R_BIAS_FBRT /128 K_ MOD _FBRT 0 1 0 R_MOD_FBRT /128 R_MOD_FBRT /128 R_MOD_FBRT /128 R_MOD_FBRT /128 R_MOD_FBRT /128 R_MOD_FBRT /128 R_MOD_FBRT /128 R_MOD_FBRT /128 BIAS (R_ DAC2) FF FF FB FB FB FB FB FF + FB FF + FB FF + FB FF + FB
[AK2572]
MOD (R_ DAC1 or R_DAC3) FF FB FF FB FB FF + FB FF + FB FB FB FF + FB FF + FB
"I/F" notation in the table indicates that the register setting can be executed via Digital I/F. [*1] Setting changes of R_BIAS_FBRT and R_MOD_FBRT are possible via Digital I/F, but APC_FB dividing coefficients K_BIAS_FBRT and K_MOD_FBRT are not affected. [*2] Register setting is possible but data is treated as "0".
< MS0290-E-01>
-22-
2004/8
ASAHI KASEI
[AK2572]
4.4 On-chip Temperature Sensor (TEMPSENS) Characteristics Characteristic of the On-chip temperature sensor (TEMPSENS) in Figure 4-14, and the relation of AD code (R_TEMP [7:1] : EEPROM address equivalent) versus Temperature relation in Table 4-10 are shown. The On-chip temperature sensor characteristic is expressed as : V [V]0.01156 * t + 1.62 [Typ.] where temperature t and output voltage V [V]. The output voltage of the detected temperature by the temperature sensor has a negative slope characteristic with - 11.56 mV/7% (Reference value by design). Output voltage from the temperature sensor is A-to-D converted by 8 bits ADC (Max. input voltage2.2 V [Typ.]) into the digital code R_TEMP [7:0] and inverted. 7 bits data of the digital code R_TEMP [7:1] is used as EEPROM address, and temperature compensation data for Bias current (E_BIAS_TC) and Modulation current (E_MOD_TC) are read out. The relation of Temperature and A-to-D converted code is expressed as : 8 bits AD code : R_TEMP7:0255int(- 1.334*t +188.3) [Typ.] 7 bits AD code : R_TEMP7:1127int(- 0.667*t +94.0) [Typ.] Be noted that as output voltage from On-chip temperature sensor is A-to-D converted into digital code and inverted, AD code against the detected temperature of On-chip temperature sensor exhibits a positive slope characteristic. Temperature change per each 1 LSB in 8 bits AD code "R_TEMP [7:0]" is +0.75 /LSB [Typ.] and temperature change per each 1 LSB in 7 bits AD code "R_TEMP [7:1]" is +1.5 /LSB [Typ.]. Therefore temperature compensation data for Bias current (E_BIAS_TC) and Modulation current (E_MOD_TC) are written in every 1.5 increment. However, as the temperature compensation data is derived from a linear interpolation of the detected temperature by the On-chip temperature sensor (refer to Section 4.1), resolution of R_BAIS_FF and R_MOD_FF data to be loaded to DAC is 0.75 . As On-chip temperature sensor detects the chip surface temperature, temperature difference exists between the LD temperature and the detected temperature by the On-chip temperature sensor. Temperature detect error of the On-chip temperature sensor can be tuned as follows : (1) Slope calculation at 2 different temperature points : Read the TEMPSENS output (TEMPMON) or the A-to-D converted code (R_TEMP) at 2 different temperature points and calculate the slope characteristic. It can adjust and correct the characteristics including the error on the slope of the On-chip temperature sensor. (2) Tuning at a single temperature point : Read the A-to-D converted code (R_TEMP) while LD adjustment is made, and calculate the AD code at a given temperature, based on the +0.75 / LSB slope characteristic. It cannot compensate the error of On-chip temperature sensor in this method.
Figure 4-14 On-chip TEMPSENS Characteristics [Typ.]
2.5 2.0 1.5 1.0 0.5 0.0 -40 -20 0 20 40 60 80 100 120
Output Voltage V [V]
Temperature t []
< MS0290-E-01>
-23-
2004/8
ASAHI KASEI
[AK2572]
Table 4-10 Relation between R_TEMP7:1 and detected temperature of the On-chip temperature sensor [Typ.] R_TEMP Temperature R_TEMP Temp. R_TEMP Temp. R_TEMP Temp. 7:1 [] 7:1 [] 7:1 [] 7:1 [] 0 - 50.2 32 - 2.2 65 45.7 96 93.7 1 - 48.7 33 - 0.7 66 47.2 97 95.2 2 - 47.2 34 0.8 67 48.7 98 96.7 3 - 45.7 35 2.3 68 50.2 99 98.2 4 - 44.2 36 3.8 69 51.7 100 99.7 5 - 42.7 37 5.3 70 53.2 101 101.2 6 - 41.2 38 6.8 71 54.7 102 102.7 7 - 39.7 39 8.3 72 56.2 103 104.2 8 - 38.2 40 9.8 73 57.7 104 105.7 9 - 36.7 41 11.3 74 59.2 105 107.2 10 - 35.2 42 12.8 75 60.7 106 108.7 11 - 33.7 43 14.3 76 62.2 107 110.2 12 - 32.2 44 15.8 77 63.7 108 111.7 13 - 30.7 45 17.3 78 65.2 109 113.2 14 - 29.2 46 18.8 79 66.7 110 114.7 15 - 27.7 47 20.3 80 68.2 111 116.2 16 - 26.2 48 21.8 81 69.7 112 117.7 17 - 24.7 49 23.3 82 71.2 113 119.2 18 - 23.2 50 24.8 83 72.7 114 120.7 19 - 21.7 51 26.3 84 74.2 115 122.2 20 - 20.2 52 27.7 85 75.7 116 123.7 21 - 18.7 53 29.2 86 77.2 117 125.2 22 - 17.2 54 30.7 87 78.7 118 126.7 23 - 15.7 55 32.2 88 80.2 119 128.2 24 - 14.2 56 33.7 89 81.7 120 129.6 25 - 12.7 57 35.2 90 83.2 121 131.1 26 - 11.2 58 36.7 91 84.7 122 132.6 27 - 9.7 59 38.2 92 86.2 123 134.1 28 - 8.2 60 39.7 93 87.7 124 135.6 29 - 6.7 61 41.2 94 89.2 125 137.1 30 - 5.2 62 42.7 95 90.7 126 138.6 31 - 3.7 63 44.2 65 92.2 127 140.1 [*] When writing APC_FF data into EEPROM, be noted that AD code data (EEPROM address equivalent where APC_FF data is stored) becomes larger when detected temperature of the On-chip temperature sensor is higher (The relation of detected temperature of the On-chip sensor and output voltage is reversed). 4.5 Current Monitor A current multiplied by 0.012 factor of the I-DAC2 output current (Sink current) is output as Sourcing current on BIASMON-pin.
< MS0290-E-01>
-24-
2004/8
ASAHI KASEI 5. Burst Mode Operation
[AK2572]
The AK2572 is put into Burst mode support operation by setting RE_BURST_SET"1". When the Burst mode operation is enabled, do not use APC_FB function. Control the LD current by APC_FF function only (RE_APC_FF_SET"3", RE_APC_FB_SET"0"), and OPTALM and CURRALM should not be selected as the target alarm on TXFAULT-pin (RE_OPTALM_SET"0", RE_CURRALM_SET"0"). Figure 5-1 Burst Mode Operation
Burst ON (Active) Burst Signal (BURST-pin) Burst OFF (Inactive)
I-DAC1, I-DAC2, V-DAC3 Temperature Detection APC_FF Operation R_DACx (x=1~3) EXTALM1 EXTALM2 TEMPALM
ON (Output Current / Voltage) ON ON (Update Data) Hold Data
61ns [typ]
ON (Output Current / Voltage) ON ON (Update Data) Update Data ON ON
ON/OFF ON
ON
(1) Alarm mask function EXTALM1 and EXTALM2 can be masked for 61 ns [Typ.] at the rising edge of Burst signal by RE_BURST_ALM setting. By enabling this masking operation, EXTALM1 and EXTALM2 for TXFAULT-pin output (Logical "OR" function of alarms set by EEPROM / Register) is masked but output to status register R_TXFLT_ST is not masked and ALM detect result is always retained in that register. (2) APC operation masking function Updating APC_FF data (R_BIAS_FF, R_MOD_FF) and temperature detection by the On-chip temperature sensor are always executed. DAC setting data (R_DACx [x1~3]) are updated during the Burst OFF. During the Burst ON, DAC setting data are not updated but the updated data made during the previous Burst OFF period is held. 5. 1 Power Leveling 1 In Power Leveling [1] mode, the data to be loaded to register (R_MOD_FF) from one of two patterns of the Modulation current temperature compensation data which are retained in EEPROM is selected by Hardware pin control (MOD_CTRL-pin) and it can be used as APC_FF data. EXTALM2 / MOD_CTRL-pin becomes MOD_CTRL control pin when both RE_PWR_LVL1_SET and RE_SFP_SET are set to "1", and Power Leveling [1] function is available. EEPROM data is set to each DAC by MOD_CTRL-pin as shown in Table 5-1.
< MS0290-E-01>
-25-
2004/8
ASAHI KASEI
[AK2572]
Table 5-1 EEPROM Address Space in Power Leveling [1] RE_MODV_SEL 1 0 MOD_CTRL-pin H L H L EEPROM Device Address Address DAC E_MOD_TC [2] A0h 00h ~ 7Dh [*] V-DAC3 I-DAC1 E_MOD_TC [1] A4h 00h ~ 7Fh V-DAC3 I-DAC1 E_BIAS_TC A4h 80h ~ FFh I-DAC2 I-DAC2 I-DAC2 I-DAC2 E_EXTRA_TC A6h 00h ~ 1Fh I-DAC1 I-DAC1 V-DAC3 V-DAC3 [*] Since Write Protect control register is allocated at "Device AddressA0h / Address7Eh, 7Fh", E_MOD_TC [2] has 126 address locations. Therefore E_MOD_TC [2] has 2 fewer address locations as compared with E_MOD_TC [1] and E_BIAS_TC. So the linear interpolation of E_MOD_TC [2] is executed as follows : R_MOD_FF(z)E_MOD_TC2(x1)E_MOD_TC2(x)E_MOD_TC2(x1)xR_TEMP [0] / 2 when zR_TEMP [7:0]0 ~ 5, E_MOD_TC(x)E_MOD_TC(x1)E_MOD_TC(0) where the detected temperature data is R_TEMP [7:0]z2x+5,2x+4, R_TEMP [7:1]x, E_MOD_TC[2] as E_MOD_TC2(x) and the obtained data by a linear interpolation is R_MOD_FF(z). 5. 2 Power Leveling [2] In Power Leveling [2] mode, the data to be loaded to register (R_BIAS_FF, R_MOD_FF) can be selected by R_PWR_SEL setting among 4 patterns of Bias current and Modulation current temperature compensation data that are retained in EEPROM. Power Leveling [2] is enabled by setting RE_PWR_LVL1_SET"0" and RE_PWR_LVL2_SET"1". When the write protect is released (WP-pin"H" and R_WP_CTRL"0"), R_PWR_SEL [1:0] data at "Device AddressA8h / Address2Fh" can be altered in Self-Operation Mode. When Power Leveling [2] is enabled, a linear interpolation of the temperature compensation data is executed by using R_TEMP [7:3], R_TEMP [2:0] and the data in EEPROM as shown in Table 5-2. R_BIAS_FF(z)E_BIAS_TCn(y1)E_BIAS_TC n(y)E_BIAS_TCn(y1)xR_TEMP [2:0] / 8 R_MOD_FF(z)E_MOD_TCn(y1){E_MOD_TCn(y)E_MOD_TCn(y1)}xR_TEMP [2:0] / 8 when y0 (R_TEMP [7:0]z0~7), E_BIAS_TCn(y)E_BIAS_TCn(y1)E_BIAS_TCn(0) and E_MOD_TCn(y)E_MOD_TCn(y1)E_MOD_TCn(0). where the detected temperature data R_TEMP [7:0]z8y, 8y+1, , 8y+7, R_TEMP [7:3]y, the temperature compensation data retained in EEPROM is E_BIAS_TCn(y), E_MOD_TCn(y), n0~3 and the obtained data by a linear interpolation is R_BIAS_FF(z), R_MOD_FF(z) respectively. Table 5-2 EEPROM Address Space in Power Leveling [2] RE_ PWR_LVL2_SET"0" RE_ PWR_LVL2_SET"1" R_TEMP 7:1 Data Address RE_PWR_SEL R_TEMP 7:3 Data 0 00h ~ 1Fh E_MOD0_TC 1 00h ~ 1Fh E_MOD1_TC 00h ~ 7Fh E_MOD_TC 00h ~ 7Fh 2 00h ~ 1Fh E_MOD2_TC 3 00h ~ 1Fh E_MOD3_TC 0 00h ~ 1Fh E_BIAS0_TC 1 00h ~ 1Fh E_BIAS1_TC 00h ~ 7Fh E_BIAS_TC 80h ~ FFh 2 00h ~ 1Fh E_BIAS2_TC 3 00h ~ 1Fh E_BIAS3_TC
Address 00h ~ 1Fh 20h ~ 3Fh 40h ~ 5Fh 60h ~ 7Fh 80h ~ 9Fh A0h ~ BFh C0h ~ DFh E0h ~ FFh
< MS0290-E-01>
-26-
2004/8
ASAHI KASEI
[AK2572]
6. Alarm Function In Table 6-1, the outline of the AK2572 Alarm (ALM) functions such as TEMPALM, OPTALM, CURRALM, EXTALM1 and EXTALM2, and TXFAULT output function where alarms to be selected by EEPROM/Register setting are logically OR-ed, are listed. Table 6-1 ALM Function Outlines ALM TEMPALM Condition to output alarm Detect time [Typ.] Note
When detected temperature equivalent value Temp. sense period=64ms 64 ms exceeds ALM set value (E_TEMPALM) Set by RE_TEMPALM_SET When monitor PD input voltage becomes lower Holding APC FB value 5 s [*] OPTALM than ALM set value (RE_OPTALM) Set by RE_OPTALM_SET When a current to be set to DAC exceeds ALM set 125 s CURRALM Set by RE_CURRALM_SET value (RE_CURRALM_BIAS / MOD) EXTALM1 When same polarity ALM signal is input on Set by RE_EXTALM1_SET 1 s EXTALM2 EXTALM1/2-pin as set by RE_EXTALM1/2_POL Set by RE_EXTALM2_SET Automatically shutdown When any of the ALMs is detected as target alarms Depend on when any target alarm is available on TXFAULT-pin output which are set by the detected TXFAULT detected and RE_SFP_SET EEPROM / Register setting (Refer to note above in target alarm "0" this table) [*] The detect time does not include the delay time caused by a time constant of external Rpd and Cpd.
6.1 TEMPALM TEMPALM is generated when the following relation is established after digitally comparing the A-to-D converted temperature sensor output value (R_TEMP [7:0]) with the ALM set value (R_TEMPALM) : R_TEMPE_TEMPALM 6.2 OPTALM 1/3, 1/4, 1/6 or 1/7 value of the APC target value (apc_ref) can be set as OPTALM set value (optalm_ref) by RE_OPTALM setting. OPTALM detect is done by an analog comparator and it is generated when the following relation is established vpdoptalm_ref 6.3 CURRALM CURRALM is generated when one of the following 3 conditions is met after digitally comparing DAC setting value for Modulation current (R_DAC1 [I-DAC1 set value] or R_DAC3 [V-DAC3 set value]) or DAC setting value for Bias current (R_DAC2 [I-DAC2 set value]) with the CURRALM setting value (R_CURRALM_BIAS, R_CURRALM_MOD): R_DAC2 (Upper 4 bits)R_CURRALM_BIAS or R_DAC1(Upper 4 bits)R_CURRALM_MOD, or R_DAC3(Upper 4 bits)R_CURRALM_MOD Alarm threshold values R_CURRALM_BIAS and R_CURRALM_MOD can be set in accordance with the LD temperature characteristic (Set by approximately every 6 step with the data in E_CURRALM_BIAS_TC, E_CURRALM_MOD_TC, Refer to Table 9-3). CURRALM is also generated when either of R_DAC1 (R_DAC3) or R_DAC2 becomes its full code (FFh). When a shutdown request is made, CURRALM is set to "Inactive" polarity. 6.4 EXTALM1, EXTALM2 When the same polarity ALM signal is input on EXTALM1-pin as set by RE_EXTALM1_POL, EXTALM1 detection is made. On the other hand, when the same polarity ALM signal is input on EXTALM2 / MOD_CTRL-pin as set by RE_EXTALM2_POL, EXTALM2 detection is made if RE_PWR_LVL1_SET"0" or RE_SFP_SET"0" (EXTALM2 / MOD_CTRL -pin is set to EXTALM2-pin) When RE_EXTALM1/2_POL"0", the ALM detect polarity of "H" at EXTALM1/2-pin is set. When RE_EXTALM1/2_POL"1", the ALM detect polarity of "L" at EXTALM1/2-pin is set. -27-
< MS0290-E-01>
2004/8
ASAHI KASEI
[AK2572]
6. 5 TXFAULT 6.5.1 Target Alarm Setting of TXFAULT Output As shown in Table 6-2, target Alarms (ALMs) available on TXFAULT output can be selected by EEPROM / Register setting. Logical "OR" function of the selected ALMs becomes TXFAULT output signal. Table 6-2 Target ALM Setting of TXFAULT Output Device Address / Address Status register Target ALM Mask setting [*1] Note (A8h / 19h) [*2] EEPROM Register R_TXFLT_ST [3] RE_EXTALM2_SET5 EXTALM2 [*3] R_TXFLT_ST [2] RE_EXTALM1_SET4 EXTALM1 A6h / 65h A8h / 05h CURRALM RE_CURRALM _SET3 R_TXFLT_ST [1] RE_OPTALM _SET2 OPTALM R_TXFLT_ST [0] TEMPALM RE_TEMPALM_SET7 A6h / 66h A8h / 06h R_TXFLT_ST [4] *1Logical "OR" function of those ALMs, where corresponding bits are set by "1" in mask setting by EEPROM / Register, becomes TXFAULT output signal. *2When ALM is detected, "1" is written in the corresponding bit of the ALM.status register. *3When RE_PWR_LVL1_SET"0" or RE_SFP_SET"0", EXTALM2 / MOD_CTRL-pin is set as EXTALM2 input pin and EXTALM2 function is enabled. 6.5.2 Operation at TXFAULT Detection Operation at TXFAULT detection differs by RE_SFP_SET setting. Operation at different settings is listed in Table 6-3. When at RE_SFP_SET"0", any of the ALMs being set by EEPROM / Register is detected, TXFAULT signal is generated and "H" output is held and DAC output is put into shutdown condition. But when a shutdown request is made via TXDIS-pin, a previous TXFAULT output level before the shutdown request is kept and even if any ALM is detected during the shutdown, TXFAULT signal is not output. When the shutdown request is released (transition of "L" to "H") via TXDIS-pin, release of TXFAULT (TXFAULT output is "L") is made. For more details, please refer to section "7. Shutdown Control". DAC output is not shutdown during the Adjustment Mode even if TXFAULT is detected. When at RE_SFP_SET"1", any of the ALMs being set by EEPROM / Register is detected, TXFAULT signal is generated (TXFAULT output is "H"), when all selected ALMs are cleared, TXFAULT is also cleared (TXFAULT output is "L"). When the shutdown condition is set, CURRALM is forced to "Disabled output" state. Table 6-3 TXFAULT Operation Shutdown Logical "OR" of RE_SFP_SET request via target ALM for TXDIS-pin TXFAULT 0 0 1 0 1 x 1 0 1 x x
TXFAULT 0 1 (Hold) Hold the previous TXFAULT level just before shutdown request Logical "OR" of target ALMs for TXFAULT Logical "OR" of target ALMs for TXFAULT
Operation Normal operation Shutdown Shutdown Normal operation Shutdown
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2004/8
ASAHI KASEI 7. Shutdown Control 7.1 Shutdown Operation The AK2572 can be put into the shutdown condition by setting TXDIS-pin to "H". The condition for shutdown in Table 7-1, and operation during shutdown in Table 7-2 are shown.
[AK2572]
Table 7-1 Shutdown Condition TXDIS RE_SFP_SET TXFAULT Operation Note 0 Normal operation 0 0 1 Shutdown Operation at TXFAULT detection for SFP support 1 x Normal operation 1 x x Shutdown Shutdown request via TXDIS-pin Table 7-2 Operation during Shutdown Function Operation during Shutdown Note I-DAC1,2 output Hi-Z [*] V-DAC3 output 0.2 V [Max.] [*] Based on the detected temperature, temperature compensation data for I-DAC APC and V-DAC are updated. But I-DAC output is in Hi-Z state and V-DAC output Feed Forward voltage is 0.2 V [Max.] During shutdown requested via TXDIS, a value just before the shutdown is held. APC During shutdown requested by TXFAULT (RE_SFP_SET"0"), a value just Feed Back before the shutdown is held and it is reset at shutdown release by TXDIS. ALM Normal operation (CURRALM is set to " Disabled output" state) At RE_SFP_SET ="0", a value just before the shutdown is held. TXFAULT At RE_SFP_SET ="1", logical "OR" function of the selected ALMs is output. [*] DAC output (I-DAC1 or V-DAC3), which is selected as EXTRA_DAC, is not shutdown. 7.2 Operation at Shutdown Release Since the AK2572 continues its temperature detection and APC feed forward operation even during the shutdown, current value that is set by Feed Forward function is temperature compensated even if any temperature difference occurs before or after the shutdown. On the other hand, whether a value just before the shutdown is held or an initial value is set as APC Feed Back data (R_APC_FB) can be selected by RE_TEMP_DET setting. When to hold a value just before the shutdown, a temperature at shutdown release (R_TEMP) and a temperature just before shutdown (to be retained at R_TEMP_STDW) are compared. If the difference is larger than the set value (RE_TEMP_WIN), namely, when the following relation is satisfied, ABS(R_TEMP-R_TEMP_STDW)RE_TEMP_WIN, a function to set R_APC_FB to initial value is activated so that an excess power emission of LD and a turn-on delay of LD are eliminated. As initialization of R_APC_FB is executed with being based on the detected temperature just before shutdown release, a turn-on operation is accelerated if the initial setting function of APC_FB is selected (RE_APC_INIT_SET"1"). In Table 7-3, R_APC_FB values at shutdown release are listed. Table 7-3 R_APC_FB Values at Shutdown Release RE_ TXRE_ Temperature R_APC_FB SFP_SET FAULT TEMP_DET difference 0 x Initial value 0 0 Held value 0 1 1 Initial value 1 x x Initial value 0 x Initial value 0 Held value 1 x 1 1 Initial value
Note ABS(TEMP-TEMP_STDW)TEMP_WIN ABS(TEMP-TEMP_STDW)TEMP_WIN Shutdown released by TXDIS ABS(TEMP-TEMP_STDW)TEMP_WIN ABS(TEMP-TEMP_STDW)TEMP_WIN
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2004/8
ASAHI KASEI 8. Start-Up Setting in SFP Support Mode 8.1 TXFAULT Detection at Power-Up and after Release from Shutdown
[AK2572]
8.1.1 OPTALM In SFP support mode setting (RE_SFP_SET"0"), a mask time can be programmed for TXFAULT detection by OPTALM during the shutdown release so that a time constant delay derived from the external Rpd and Cpd for detection of the averaged monitor-PD current at the turning-on of LD must be taken into consideration. Block diagram in Figure 8-1, and pre-settable mask time relation in Table 8-1 are shown. In the AK2572, the delay time can be shortened by accelerated start-up setting which is made by initial value setting function of R_APC_FB and so on. But when OPTALM is selected as one of the TXFAULT target ALMs, and a mask time is set to be shortened, be noted that LD optical power will not reach the expected level within the mask time and it may be shutdown through OPTALM detection to TXFAULT control sequence if initial set value of APC_FF or APC_FB is far off. Figure 8-1 OPTALM Detection Block Diagram
LD
Monitor PD PDIN
PDGAIN setting (RE_PDGAIN)
APC_ COMP vpd
DIGITAL FILTER
APC Feedback value (R_APC_FB)
PDGAIN Cpd Rpd OPALM setting (R_OPTALM) OPTALM _COMP ATT OPTALM threshold (optalm_ref)
TXFAULT CONTROL
vapc_ref APC target (R_APC_TRGT)
A time constant delay at shutdown release derived from the external Rpd and Cpd must be taken into consideration
DAC_APC
Table 8-1 Time to Valid TXFAULT Detection by OPTALM RE_ RE_TIMER RE_APC_ RE_APC Mask time for TXFAULT SFP_SET _OPTALM INIT_SET _FF_SET detection by OPTALM 0 x x 160 ms [Typ.] 0 00, 01, 10 160 ms [Typ.] 0 1 x 11 2 ms [Typ.] 1 x 2 ms [Typ.] 1 x x x 0 ms
Note
Accelerated start-up setting Accelerated start-up setting Non-support SFP
8.1.2 EXTALM1, EXTALM2 In SFP support mode setting (RE_SFP_SET"0"), a mask time can be set for TXFAULT detection by EXTALM1 and EXTALM2 at the shutdown release. In Table 8-2, a delay time relation to be set is shown. Table 8-2 Time to Valid TXFAULT Detection by EXTALM1, EXTALM2 RE_TIMER_EXTALM1 Mask time for TXFAULT detection Note RE_SFP_SET by EXTALM1, EXTALM 2 RE_TIMER_EXTALM2 0 0 ms 0 1 2 ms [Typ.] 1 X 0 ms Non-support SFP
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2004/8
ASAHI KASEI 8.2 At Power-On (at TXDIS="L") Start-up sequence at power-onat TXDIS"L" is shown in Figure 8-2. Figure 8-2 Start-up Sequence at Power-on (at TXDIS="L")
[AK2572]
VDD
TXDIS 2ms [Typ.] LD Current APC FF value or APC FB initial value APC FF value APC FB initial procedure Power On Reset Initialization TXFAULT enable without OPTALM (When not to set accelerated start-up sequence) t_init: 160ms [Typ.] TXFAULT with OPTALM enable ALM operation TXFAULT with OPTALM enable (When to set accelerated start-up sequence)
APC Feedback Normal operation
8.3 At Power-On (at TXDIS"H") Start-up sequence at power-on (at TXDIS"H") is shown in Figure 8-3. Figure 8-3 Start-up Sequence at Power-on (at TXDIS"H")
VDD
TXDIS 2ms [Typ.] LD Current APC FF value or APC FB initial value APC FF value APC FB initial procedure Power On Reset Initialization TXFAULT enable without OPTALM (When not to set accelerated start-up sequence) t_init: 160ms [typ] TXFAULT with OPTALM enable ALM Operation TXFAULT with OPTALM enable (When to set accelerated start-up sequence)
APC Feedback Normal operation
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2004/8
ASAHI KASEI 8.4 At TXDIS Detection / Release TXDIS detection / release sequence is shown in Figure 8-4. Figure 8-4 TXDIS Detection / Release Sequence
[AK2572]
VDD 10s [Min.] TXDIS
TXFAULT TXFAULT operation when accelerated start-up sequence is selected is same as that when no temperature difference exists Both of the temperature at Rising and Falling edge of TXDIS signal are compared TXFAULT disable 2ms [Typ.] APC Feedback Normal operation TXFAULT enable without OPTALM TXFAULT with OPTALM enable No temperature difference exists
LD Current
APC FB initial procedure t_off10s t_on1ms
Temperature difference exists TXFAULT with OPTALM enable
t_init:160ms[Typ.]
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2004/8
ASAHI KASEI 8.5 At TXFAULT Detection / Release TXFAULT detection / release sequences are shown in Figure 8-5 and Figure 8-6. Figure 8-5 TXFAULT Detection / Release Sequence (When FAULT is released by TXDIS reset)
VDD
[AK2572]
TXDIS t_reset: 10s [Min.] FAULT
TXFAULT
2ms [Typ.]
TXFAULT with OPTALM enable (When to set accelerated start-up sequence)
LD Current
t_init: 160ms[Typ.] Depend on the detcted ALM (Refer to Table 6-1)
TX_FAULT enable without OPTALM
TXFAULT with OPTALM enable
Figure 8-6 TXFAULT Detection / Release Sequence (When FAULT is not released)
VDD
TXDIS t_reset: 10s[Min.]
FAULT
TXFAULT
LD Current
t_fault Depend on the detcted ALM (Refer to Table 6-1) TXFAULT detection with OPTALM When to set accelerated start-up sequence: 2ms [Typ.] When not to set accelerated start-up sequence: 160ms [Typ.] TXFAULT detection with EXTALM1,2 2ms [Typ] or 0ms (Set by RE_TIMER_EXTALM1,2)
< MS0290-E-01>
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2004/8
ASAHI KASEI
[AK2572]
9. Digital Interface Configuration 9.1 Memory Configuration EEPROM and Register configuration is shown in Figure 9-1. Access to EEPROM and Register is executed via 2-wire Digital Interface (I/F). Figure 9-1 Memory Configuration
Device Address-1 Device Address-2 Address 0000 0000 ~ 0111 1101 1010 000 0111 1110 0111 1111 1000 0000 ~ 1111 1111 0000 0000 ~ 1111 1111 0000 0000 ~ 0111 1111 1000 0000 (A4h) ~ 1111 1111 0000 0000 ~ 0001 1111 0010 0000 ~ 0011 1111 0100 0000 ~ 0101 1111 0110 0000 ~ 0111 1111 (A6h) 1000 0000 ~ 1111 1111 0000 0000 ~ 1111 1110
Contents User Area or Temperature Compensation Data for Imod [2]
(1K) [1] USER AREA for SFP_MSA support when RE_SFP_SET="0" [2] E_MOD_TC2 for Power Leveling [1] when RE_SFP_SET="1" and RE_PWR_LVL1_SET="1"
Write Protect Control (2Address) No Memory
(1K) Power Leveling [1] (Select the data for Imod by MOD_CTRL-pin) is available when RE_SFP_SET="1" and RE_PWR_LVL1_SET="1"
(A0h)
1010 (A2h)
001
No Memory
(2K) Power Leveling [2] is available when RE_PWR_LVL2_SET="1" (RE_PW R_LVL1_SET="0" Selected by RE_PWR_SEL[1:0]
Temperature Compensation Data for Imod
[E_MOD_TC(1K): I-DAC1 or V-DAC3]
1010
010
Temperature Compensation Data for Ibias
[E_BIAS_TC(1K): I-DAC2]
I-BIAS0 I-BIAS1 I-BIAS2
I-MOD0 I-MOD1 I-MOD2 I-MOD3
Temp. Compensation Data for EXTRA DAC
[E_EXTRA_TC(256): V-DAC3 or I-DAC1] (=Not DAC for Imod)
I-BIAS3
Switch I-DAC1 and V-DAC3 by RE_MODV_SEL setting
Temperature Data for APC_FB target
[E_APC_TRGT_TC(256)]
Write Protect Control (WP)
Register A0h/7Eh R_WP_CTRL[0] (Protect Control) R_PASSW D[7:0] (Password) EEPROM A6h/7Eh E_WP_CTRL[0] (Protect Control) E_PASSWD[7:0] (Password )
1010
011
Temperature Data for CURRALM Threshold
[E_CURRALM_BIAS/MOD_TC(256)]
A0h/7Fh
Set-up Data
(256)
A6h/7Fh
No memory
(1K)
Write Protect is enable when W P-pin="L" or R_WP_CTRL[0]="1" (W P-pin setting has a higher priority than R_WP_CTRL) * Only A0h(1K) area is possible to Read when Write Protect is enable Write Protect is released when WP-pin="H" and R_W P_CTRL[0]="0" * Full access is possible when when W rite Protect is released (When R_PASSWD[7:0] via Digital I/F agree with E_PASSWD[7:0], access to R_WP_CTRL[0] becomes possible)
1010 (A8h) 1010
100
Register Operation Mode Change Command
100
1111 1111
[*] Device address is configured with Device address-1 ("1010 ""Ah") and Device address-2. Device address-2 in 3 bits Binary expression is converted into Hexadecimal code by multiplying it by 2. For example, when Device address-1"1010" and Device address-2"011", Device address becomes "A6h".
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2004/8
ASAHI KASEI 9.2 Write Protect Operation
[AK2572]
Accessible range and Device address via Digital I/F are determined by Write Protect setting as shown in Table 9-1. Table 9-1 Write Protect Operation Item R_WP_CTRL Device address ACK Access to EEPROM / Register Operation mode Page Write WP = "L" 0 1 x 1010 xxx 1010 000 1010 000 When corresponding Device address is input via Digital I/F [*1] A0h only A0h only Full Access [*2] Read only Read only Self-Operation Self-Operation Transition to any operation mode is possible Mode only Mode only Sequential write operation of EEPROM is possible in every 16 bytes. Sequential write operation of Register (Address after A8h/3Eh is folded back to A8h/00h). Sequential read operation of both EEPROM and Register is possible within the designated address area respectively. Address after A6h/FFh is folded Sequential read is possible in back to A0h/00h in EEPROM and address after accessible EEPROM area. A8h/3Fh is folded back to A8h/00h in Register. "Non-actual space" address is not skipped. WP = "H"
Sequential Read
*1 ACK signal is not returned during the writing operation into EEPROM. *2 When Write Protect is released (WP-pin"H" and R_WP_CTRL"0"), writing into R_PWR_SEL[1:0] at address = A8h / 2Fh is possible in Self-Operation Mode. About Write Protect Setting * The data for fully accessible setting (E_WP_CTRL"0", E_PASSWD"0") is programmed at AKM. (a) Write Protect operation is "ON" when WP-pin at "L". WP-pin setting has a higher priority than R_WP_CTRL (Register for Write Protect setting). (b) Write Protect operation is controlled to be "ON " or "OFF" by R_WP_CTRL when WP-pin is at "H". Access to R_WP_CTRL is possible only when R_PASSWD [7:0] (Register for Write Protect password), which is loaded via digital I/F, agrees with E_PASSWD [7:0] that is the password retained in advance. Be noted that other than "00h" should be written into E_PASSWD [7:0] to enable Write Protect. - R_WP_CTRL"0" Full access is possible - R_WP_CTRL"1" Only the area in Device address'1010 000A0h` is accessible (Read Only), especially only Write Protect control register (R_PASSWD, R_WP_CTRL) are writable Accordingly, when Self-Operation Mode is set by R_WP_CTRL"1", access to the adjusting data is executed as the following procedure, (1) Make it enable to access to R_WP_CTRL by setting the same value to R_PASSWD as is retained in E_PASSWD in advance. (2) Set R_WP_CTRL "0" to enable full access. (3) When to modify EEPROM content, shift the mode into EEPROM Access Mode and then modify data. At the Power-on or when Self-Operation Mode is set, R_PASSWD is reset to "00h" and E_WP_CTRL value is loaded to R_WP_CTRL. So, if E_WP_CTRL is set to "0", Write Protect operation is automatically released at Power-on or when Self-Operation Mode is set. Table 9-2 Write Protect Control Register / EEPROM Register EEPROM D7 D6 D5 A0h / 7Eh A6h / 7Eh A0h / 7Fh A6h / 7Fh D4 D3 D2 PASSWD D1 D0 WP_CTRL
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ASAHI KASEI 9.3 Read / Write Operation 9.3.1 Byte Write Byte Write operation is shown in Figure 9-2. Select address and then input the data to be written. Figure 9-2 Byte Write
[AK2572]
SDA
S T A R T
1010
Device Address-1
00
Device R/ Address-2 W A C K Address (MSB First)
0
A C K Data (MSB First)
0
A C K S T O P
9.3.2 Page Write Page Write operation is shown in Figure 9-3. Up to 16 bytes of data can be written at one time. In Page Write operation, the lower 4 bits of the 8 bits address are effective and the upper 4 bits data does not change. Therefore after writing data at "xxxx 1111", next address to be written is "xxxx 0000". Figure 9-3 Page Write
SDA
1010 00
Address (MSB First)
0
A C K Data (Address)
0
0
....
0
0
S Device Device R/ A T Address-1Address W C -2 K A R T
A Data (Address + 1) A C C K K
A Data (Address + n) A S C CT K KO P
9.3.3 Current Address Read Current Address Read operation is shown in Figure 9-4. Address location where data is to be read out is "most recently accessed address + 1". Figure 9-4 Current Address Read
SDA
S T A R T
1010
Device Address-1
10
Device R/ Address-2 W A C K Data (MSB First)
1
N O A C K S T O P
9.3.4 Random Read Random Read operation is shown in Figure 9-5. When to execute Random Read operation, assign an address to be read out by Dummy Write operation, and issue a Read instruction. Figure 9-5 Random Read
SDA
S T A R T
1010
Device Address-1
00*
Device R/ A Address-2 W C K Address (MSB First)
0
AS CT KA R T
1010
Device Address-1
10
Device R/ A Address-2 W C K Data (MSB First)
1
N O A C K S T O P
Dummy Write
*: Don't care when Write Protect "ON"
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ASAHI KASEI
[AK2572]
9.3.5 Sequential Read Sequential Read operation is shown in Figure 9-6. After the data at the designated address is output by read instruction, next address data can be read out if ACK signal is generated without stop bit signal that is sent from a master controller Figure 9-6 Sequential Read
SDA
....
10
Data-1 (MSB First)
0
A C K Data-2
0
A C K
....
0
A C K Data-n
1
N O A C K S T O P
Device R/ A Address-2 W C K
9.3.6 Data Change Data Change timing chart is shown in Figure 9-7. Data change (SDA) is made while SCL is at "L". Figure 9-7 Data Change
SCL
SDA
DATA STABLE DATA CHANGE
9.3.7 Start / Stop Start / Stop timing chart is shown in Figure 9-8. While SCL is at "H", Start is effective by setting SDA from "H" to "L", and Stop is effective by setting SDA from "L" to "H". Figure 9-8 Start / Stop
SCL
SDA
START STOP
< MS0290-E-01>
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2004/8
ASAHI KASEI
[AK2572]
9.4 EEPROM Configuration EEPROM configuration is listed in Table 9-3. EEPROM configuration of adjustment data area is listed in Table 9-4 and Table 9-5. The access to EEPROM depends on its operation modes (Refer to Table 10-1). And the access to EEPROM is also limited by Write Protect setting (Refer to Section 9.2). < Important Notice > The adjusted data in AKM factory are stored in advance at address location (Device AddressA6h, Address60h) for the offset voltage of the On-chip temperature sensor. If such excessive temperature stress is to be applied to the AK2572 which exceeds a guaranteed EEPROM data retention conditions (for 10 years at 85), it is important to read the pre-determined data in advance and to re-write the same data back into EEPROM after an exposure to the excessive temperature environment. Even if the exposure time is shorter than the retention time, any accelerated temperature stress tests (such as baking) are performed, it is recommended to read the pre-set data first and to re-write it after the test. Access to unused address locations is not functionally guaranteed. Table 9-3 EEPROM Address Configuration Device Address Address A0h 00h (0) ~ 7Dh (125) A0h 80h (128) ~ FFh (255) A2h 00h (0) ~ FFh (255) Data (D7 ~ D0) Initial value 00h Note
User Area (1k bits) [*1] No Memory No Memory E_MOD_TC (1k bits) A4h 00 h (0) ~ 7Fh (127) 00h [*2]~[*4] Temperature Compensation Data for Imod E_BIAS_TC (1k bits) A4h 80h (128) ~ FFh (255) 00h [*2], [*3] Temperature Compensation Data for Ibias E_EXTRA_TC (256 bit) 00h [*5] A6h 00h (0) ~ 1Fh (31) Temperature Compensation Data for EXTRA DAC E_APC_TRGT_TC (256 bit) A6h 20h (32) ~ 3Fh (63) 00h [*5] Temperature Compensation Data for APC target E_CURRALM_BIAS / MOD_TC (256 bit) A6h 40h (64) ~ 5Fh (95) FFh [*5] Temperature Compensation Data for CURRALM threshold A6h 60h (96) ~ 6Ah (106) Adjustment Data (88 bit) Reserved (152 bit A6h 6Bh (107) ~ 7Dh (125) A6h 7Eh (126), 7Fh (127) Write Protect Control (16 bit) 00h *1With both RE_SFP_SET"1" and RE_PWR_LVL1"1", this area becomes setting area for Imod temperature compensation data [2] (E_MOD_TC2) of Power Leveling [1] function. *2R_TEMP (Upper 7 bits A-to-D code of the temperature sensor) and address are corresponded (1.5 /step) and then the temperature compensation data is written. *3With RE_PWR_LVL1"0" and RE_PWR_LVL2"1", these area become setting area for Ibias and Imod temperature compensation data of Power Leveling [2] function. *4With both RE_SFP_SET"1" and RE_PWR_LVL1"1", this area becomes setting area for Imod temperature compensation data [1] (E_MOD_TC1) of Power Leveling [1] function. *5Upper 5 bits of R_TEMP and address are corresponded (6.0 /step), and then the temperature compensation data is written.
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ASAHI KASEI Table 9-4 EEPROM : Adjustment Data Configuration EEPROM Address Function E_VREFTRIM [7:4] E_TEMP _OFFSET [3:0] E_PWR_SEL [7:6] E_BURST_ALM [5:4] E_BURST_SET [3] E_PWR_LVL2 _SET [2] E_SFP_SET [1] E_PWR_LVL1_SET [0] E_APC_FF_SET [7:6] E_APC_FB_SET [5:4] E_APC_INIT_SET [3] E_DAC3_GAIN [2] E_DAC2_GAIN [1] E_DAC1_GAIN [0] E_TIMER _OPTALM [6] E_EXTALM2_POL [5] E_EXTALM1_POL [4] E_TEMP_DET [3] E_DAC_SET [2:0] E_OPTALM [7:6] E_PDGAIN [5:0] E_EXTALM2_SET [5] E_EXTALM1_SET [4] E_CURRALM_SET [3] E_OPTALM_SET [2] E_TIMER _EXTALM2 [1] E_TIMER _EXTALM1 [0] E_TEMPALM_SET [7] E_TEMP_WIN [7:0] E_MODV_SEL [7] E_MOD_FBRT [6:0] E_BIAS_FBRT [6:0] E_TEMPALM [7:0] 60h 60h 61h 61h 61h 61h 61h 61h 62h 62h 62h 62h 62h 62h 63h 63h 63h 63h 63h 64h 64h 65h 65h 65h 65h 65h 65h 66h 67h 68h 68h 69h 6Ah On-chip oscillator frequency Temperature sensor offset EEPROM data switching at Power Leveling [2] EXTALM mask setting at Burst mode Burst mode setting Power Leveling [2] setting SFP_MSA support setting Power Leveling [1] setting APC FF setting APC FB setting APC_FB initial value setting V-DAC3 gain setting I-DAC2 gain setting I-DAC1 gain setting OPTALM mask time setting for SFP_TXFAULT detection EXTALM2 polarity setting EXTALM1 polarity setting Temperature difference detection at Shutdown release DAC operation setting OPTALM threshold PD gain setting EXTALM2 setting for TXFAULT EXTALM1 setting for TXFAULT CURRALM setting for TXFAULT OPTALM setting for TXFAULT EXTALM2 mask time setting for SFP_TXFAULT detection EXTALM1 mask time setting for SFP_TXFAULT detection TEMPALM setting for TXFAULT Window setting for Temperature difference detection DAC setting for Imod (Data setting for I-DAC1,V-DAC3) APC_FB dividing value for Imod APC_FB dividing value for Ibias TEMPALM threshold
[AK2572]
Bit Initial Factory 4 setting Factory 4 setting 2 2 1 1 1 1 2 2 1 1 1 1 1 1 1 1 3 2 6 1 1 1 1 1 1 1 8 1 7 7 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00h 0 0 0 0 0 0 0 00h 0 00h 00h 00h
Note
Refer to Table 5-2 0:Non-masked, 1:Masked [5]: EXTALM2, [4]: EXTALM1 0:OFF, 1:ON 0:OFF, 1:ON 0:ON, 1:OFF Refer to Table 5-1 Refer to Table 4-6 Refer to Table 4-6 0: OFF, 1: ON 0:Gain1, 1:Gain1.2/2.2 0:Gain1/2, 1: Gain1 0:Gain1/10, 1: Gain1 0:160ms, 1:2ms [Typ.] (Refer to Table 8-1) 0:"H" active, 1:"L" active 0:"H" active, 1:"L" active 0:OFF, 1:ON Refer to Section 7.2 0:OFF, 1:ON [2]: V-DAC3, [1]: I-DAC2 [0]: I-DAC1 0 : 1/3, 1: 1/4, 2 : 1/6, 3 : 1/7 Refer to Table 4-3 0:OFF, 1:ON (Target) 0:OFF, 1: ON (Target) 0:OFF, 1: ON (Target) 0:OFF, 1: ON (Target) 0:0ms , 1:2ms [Typ.] Refer to Table 8-2 0:0ms , 1:2ms [Typ.] Refer to Table 8-2 0:OFF, 1: ON (Target) Refer to Section 7.2 and Table 4-10 Refer toTable 3-4 Refer to Section 4.2.4 Refer to Section 4.2.4 Refer toTable 4-10
< MS0290-E-01>
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ASAHI KASEI
[AK2572]
Table 9-5 EEPROM : Adjustment Data Setting Map ("0" must be written where data bit is marked with "0") Address D7 D6 D5 D4 D3 D2 D1 D0 VREFTRIM TEMP_OFFSET 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h 6Ah
MODV _SEL 0 TEMPALM _SET PWR_SEL APC_FF_SET 0 TIMER_ OPTALM OPTALM 0 0 EXTALM2 EXTALM1 _SET _SET 0 0 BURST_ALM APC_FB_SET EXTALM2 EXTALM1 _POL _POL BURST _SET APC_INIT _SET TEMP _DET PDGAIN CURRALM _SET 0 TEMP_WIN MOD_FBRT BIAS_FBRT TEMPALM OPTALM _SET 0 TIMER_ EXTALM2 0 TIMER_ EXTALM1 0 PWR_LVL2 _SET DAC3 _GAIN SFP_SET DAC2 _GAIN DAC_SET PWR_LVL1 _SET DAC1 _GAIN
9.5 Register Configuration In Table 9-6 and Table 9-7, Register configuration is shown. As to the access limitations via Digital I/F, please refer to Table 9-1. Details of " R/W " column and " Form " column in Table 9-6 are described below. (1) "R/W" column R: Read only operation is possible in Adjustment Mode and in Self-Operation Mode when Write Protect operation is released. Writing the data into these Registers via Digital I/F is impossible. R/W : Read / Write operation is possible in Adjustment Mode, and Read operation is possible in Self-Operation Mode when Write Protect operation is released. Data written via Digital I/F is retained till operation mode is altered or data is modified. The AK2572 allows LD module adjustment at the product shipment by modifying the data in R/W registers. R/FW: In addition to R/W function above, Read / Write operation is possible in Self-Operation Mode when Write Protect operation is released. (2) "Form" column U : Unsigned S : Signed 2's Complement Function On-chip oscillator frequency Temperature sensor offset EEPROM data switching at Power Leveling [2] EXTALM mask setting at Burst mode Burst mode setting Power Leveling [2] setting SFP_MSA support setting Power Leveling [1] setting -40Bit Form R/W 4 U R/W 4 2 2 1 1 1 U U U U U U U R/W R/W R/W Refer to Table 5-2 [*1] Note
Table 9-6 Register Configuration Register Address R_VREFTRIM [7:4] 00h R_TEMP 00h _OFFSET [3:0] R_PWR_SEL [7:6] R _BURST_ALM [5:4] R _BURST_SET [3] R_PWR_LVL2 _SET [2] R_SFP_SET [1] R_PWR_LVL1_SET [0] < MS0290-E-01> 01h 01h 01h 01h 01h 01h
0:Non-masked, 1:Masked [5]: EXTALM2, [4]: EXTALM1 R/W 0:OFF, 1:ON R/W R/W R/W 0:OFF, 1:ON 0:ON, 1:OFF Refer to Table 5-1 2004/8
ASAHI KASEI Table 9-6 Register Configuration (Continued) Register Address Function R_APC_FF_SET [7:6] 02h APC FF setting R_APC_FB_SET [5:4] 02h APC FB setting R_APC_INIT_SET [3] 02h APC_FB initial value setting R_DAC3_GAIN [2] R_DAC2_GAIN [1] R_DAC1_GAIN [0] R_TIMER _OPTALM [6] R_EXTALM2_POL [5] R_EXTALM1_POL [4] R_TEMP_DET [3] R_DAC_SET [2:0] R_OPTALM [7:6] R_PDGAIN [5:0] R_EXTALM2_SET [5] R_EXTALM1_SET [4] R_CURRALM_SET [3] R_OPTALM_SET [2] R_TIMER _EXTALM2 [1] R_TIMER _EXTALM1 [0] R_TEMPALM_SET [7] R_TEMP_WIN [7:0] R _MODV_SEL [7] R_MOD_FBRT [6:0] R_BIAS_FBRT [6:0] R_APC_FBIV [7:0] R_APC_TRGT [4:0] R_MOD_FF [7:0] R_BIAS_FF [7:0] R_EXTRA [7:0] R_CURRALM _BIAS [7:4] R_CURRALM _MOD [3:0] < MS0290-E-01> 02h 02h 02h 03h 03h 03h 03h 03h 04h 04h V-DAC3 gain setting I-DAC2 gain setting I-DAC1 gain setting OPTALM mask time setting for SFP_TXFAULT detection EXTALM2 polarity setting EXTALM1 polarity setting Temperature difference detection at Shutdown release DAC operation setting
[AK2572]
Bit Form R/W 2 U R/W 2 U R/W 1 U R/W 1 1 1 1 1 1 1 3 2 6 1 1 1 1 1 1 1 8 1 7 7 8 5 8 8 8 4 4 U U U U U U U U U U U U U U U U U U U U U U U U U U U U R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
OPTALM threshold PD gain setting EXTALM2 setting for 05h TXFAULT EXTALM1 setting for 05h TXFAULT CURRALM setting for 05h TXFAULT 05h OPTALM setting for TXFAULT EXTALM2 mask time setting 05h for SFP_TXFAULT detection EXTALM1 mask time setting 05h for SFP_TXFAULT detection 06h Set TEMPALM for TXFAULT Window setting for 07h Temperature difference detection DAC setting for Imod (Data 08h setting for I-DAC1, V-DAC3) APC_FB dividing value for 08h Imod APC_FB dividing value for 09h Ibias 0Ah APC FB initial value 0Bh APC target setting 0Ch APC_FF value for Imod 0Dh APC_FF value for Ibias 0Eh 0Fh 0Fh EXTRA DAC value CURRALM setting for Ibias CURRALM setting for Imod -41-
Note Refer to Table 4-6 Refer to Table 4-6 0: OFF, 1: ON 0:Gain1 1:Gain1.2/2.2 0:Gain1/2, 1: Gain1 0:Gain1/10, 1: Gain1 0:160ms, 1:2ms [Typ.] (Refer to Table 8-1) 0:"H" active, 1:"L" active 0:"H" active, 1:"L" active 0:OFF, 1:ON Refer to Section 7.2 0:OFF, 1:ON [2] : V-DAC3, [1] : I-DAC2 [0] : I-DAC1 0:1/3, 1:1/4, 2:1/6, 3:1/7 Refer to Table 4-3 0:OFF, 1:ON (Target) 0:OFF, 1: ON (Target) 0:OFF, 1: ON (Target) 0:OFF, 1: ON (Target) 0:0ms , 1:2ms [Typ.] Refer to Table 8-2 0:0ms , 1:2ms [Typ.] Refer to Table 8-2 0:OFF, 1: ON (Target) Refer to Section 7.2 and Table 4-10 Refer to Table 3-4 Refer to Section 4.2.4 Refer to Section 4.2.4
R/W Refer to Table 4-10 [*2] R/W Refer to Table 4-4 R/W I-DAC1 or V-DAC3 R/W I-DAC2 V-DAC3 or I-DAC1 R/W (DAC isn't for Imod) R/W R/W Refer to Section 6.3 Refer to Section 6.3
2004/8
ASAHI KASEI Table 9-6 Register Configuration (Continued) Register Address Function Bit Form R/W Temperature equivalent value R_TEMP [7:0] 10h 8 U R (AD code of temperature sensor) R_TEMP Temperature equivalent value at 14h 8 U R _STDW [7:0] just before Shutdown request R_TXFLT_ST [4:0]
[AK2572]
Note Refer to Table 4-10 Refer to Section 7.2 and Table 4-10 1: Active, 0: Inactive [4] TEMPALM [3] EXTALM2 [2] EXTALM1 [1] CURRALM [0] OPTALM [*3] [*3] [*3] [7]Sign of APC_FB [*2] [6:0] Upper 7bits of APC_FB 001:Self-Operation Mode 010:Adjustment Mode 100:EEPROM Access Mode
19h
Alarm status
5
U
R
R_DAC1 [7:0] R_DAC2 [7:0] R_DAC3 [7:0] R_APC_FB [7:0] R_MODE [2:0] AKM test
1Bh 1Ch 1Dh 1Eh 1Fh 28h~2Bh 2Eh
I-DAC1 value I-DAC2 value V-DAC3 value APC_FB value Operation mode For AKM test
8 8 8 8 3
U U U S U
R R R R R
R_PWR EEPROM data switching at 2Fh 2 U R/FW Refer to Table 5-2 [*1] _SEL [1:0] Power Leveling [2] *1 Finally modified value in either R_PWR_SEL [7:6] (R/W) at address "01h" or R_PWR_SEL [1:0] (R/FW) at address "2Fh" becomes valid R_PWR_SEL set value and is updated and retained in R_PWR_SEL at both address locations. And with R_PWR_LVL1_SET"0" and R_PWR_LVL2_SET"1", Power Leveling[2] is available and write in Self-Operation Mode can be executable only to R_PWR_SEL [1:0] (R/WF) at address "2Fh" when Write Protect operation is released. *2 Data configuration is shown in Figure 9-9. Register is configured with the signed 9 bits data, but Read / Write operation via Digital I/F is processed in 8 bits configuration. *3 In Bias current setting DAC and Modulation current setting DAC, Digital code for DAC is given as following equation and negative value at R_DACx is set to "0". R_DACxR_DACx_FFR_DACx_FB (x1 ~ 3) Figure 9-9 Signed Register Configuration Register (9 bits 2's complement) Sign D8 D7 D6 D5 Body (8 bits) D4 D3 D2 D1 D0
Read data via Digital I/F (R_APC_FB) (Sign + Body [MSB 7 bits]) Write data via Digital I/F R_APC_FBIV (Body 8 bits, Negative value cannot be written
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ASAHI KASEI Table 9-7 Register Map Address D7 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h ~13 14h 15h ~ 18 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h ~ 27 28h ~ 2Bh 2Ch 2Dh 2Eh 2Fh
MODV _SEL MOD_FF BIAS_FF EXTRA CURRALM_BIAS TEMP TEMP_STDW TXFLT_ST STATUS DAC1 DAC2 DAC3 R_APC_FB [8:1] CURRALM_MOD 0 TEMPALM _SET PWR_SEL APC_FF_SET 0 TIMER_ OPTALM OPTALM 0 0 EXTALM2 EXTALM1 _SET _SET 0 0
[AK2572]
D6
VREFTRIM
D5
D4
D3
BURST _SET APC_INIT _SET TEMP _DET PDGAIN CURRALM _SET 0 TEMP_WIN MOD_FBRT BIAS_FBRT APC_FBIV
D2
PWR_LVL2 _SET DAC3 _GAIN
D1
SFP_SET DAC2 _GAIN DAC_SET
D0
PWR_LVL1 _SET DAC1 _GAIN
TEMP_OFFSET BURST_ALM APC_FB_SET
EXTALM2 EXTALM1 _POL _POL
OPTALM _SET 0
TIMER_ EXTALM2 0
TIMER_ EXTALM1 0
APC_TRGT

MODE
Reserved (For AKM test)
Reserved (For AKM test) PWR_SEL
< MS0290-E-01>
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ASAHI KASEI
[AK2572]
10. Operation Modes The AK2572 has the following 3 operation modes Self-Operation Mode where temperature compensation operation is automatically executed in accordance with EEPROM setting, Adjustment Mode where each LD adjustment is made and EEPROM Access Mode where adjusting data is written into EEPROM. 10.1 Self-Operation Mode With the On-chip oscillator, those functions as temperature detection, read out of temperature compensation data from EEPROM and LD drive current setting by APC control, are automatically executed. At the Power-on, the AK2572 is put into Self-Operation Mode. 10.2 Adjustment Mode This is a mode to adjust each LD characteristic. When the device is put into this mode, the temperature compensation operation stops and various setting data can be written via Digital I/F. Adjustment is made by accessing the internal Register via Digital I/F. 10.3 EEPROM Access Mode This is a mode to write LD adjusting data and various set-up data into EEPROM. 10.4 Mode Control In Figure 10-1, "Mode Transition Flow Chart" is shown. Transition to each mode is controlled by some commands (Refer to Section 10.5) via Digital I/F. Access to Digital I/F is prohibited for 2 msec [Typ.] after the transition to Self-Operation Mode is made (After the Power-on and after issuing Operation mode change command). Accessible EEPROM / Register via Digital I/F in each operation mode is listed in Table 10-1. Figure 10-1 Mode Transition Flow Chart
Hold data in Register Adjustment Mode Start-up Power ON Self-Operation Mode Start-up Shutdown EEPROM Access Mode Shutdown
Table 10-1 Operational Conditions in Each Mode R_WP_CTRL EEPROM Register Operation mode WP-pin [*1] Read Write Read Write [*2] x x x L Fixed at Self-Operation Mode x x x [*1] 1 Fixed at Self-Operation Mode [*2] x x [*1][*3][*5] Self-Operation Mode H 0 [*4] x [*5] [*6] Adjustment Mode x x [*5] EEPROM Access Mode [*1] If WP-pin"H", writing into R_PASSWD is always possible in Self-Operation Mode. When R_PASSWD and E_PASSWD agree, writing into R_WP_CTRL becomes possible. [*2] When Write Protect is enabled (WP-pin"L" or R_WP_CTRL"1"), Self-Operation Mode is set as the operating mode and Read Only operation is possible at Device Address"A0h". [*3] When Write Protect is released, writing into R_PWR_SEL[1:0] at Address"A8h / 2Fh" in Self-Operation Mode is possible. Power Leveling[2] is enabled at R_PWR_LVL1_SET"0"R_PWR_LVL2_SET"1". [*4] Full access is possible when Write Protect is released (WP-pin"H" and R_WP_CTRL"0"). [*5] "Operation Mode Change command " can be executed. [*6] In Adjustment Mode, when R_SFP_SET is modified, the access via Digital I/F cannot be made for 80 msec [Typ.] from the data modification. < MS0290-E-01> -442004/8
ASAHI KASEI 10.5 Operation Mode Change Commands Transition to each mode is made by Operation Mode Change command via Digital I/F. In Table 10-2, a list of Operation Mode Change commands is shown. Table 10-2 Operation Mode Change Commands Device Address R/W Address Data 1010 100 W 1111 1111 1010 0000 1010 100 W 1111 1111 1010 0111 1010 100 W 1111 1111 1010 1110
[AK2572]
Operation mode set by command Self-Operation Mode Adjustment Mode EEPROM Access Mode
10.6 Mode Protection In order to protect from shifting into Adjustment Mode or EEPROM Access Mode due to un-expected external hazard such as noise during Self-Operation Mode, WP-pin = "L" or R_WP_CTRL"1" should be set to inhibit the above erroneous operation.
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ASAHI KASEI 11. Example of Adjusting Sequence Adjusting sequence example is shown in Table 11-1.
[AK2572]
Table 11-1 Example of Adjusting Sequence (for Continuous mode) Item Contents 1 Transition to After releasing the Write Protection, issue a command to make a transition Adjustment Mode into Adjustment Mode via Digital I/F. 2 Set APC_FB in Set R_APC_FB_SET="0" R_APC_FF_SET="3", and Bias current and open-loop operation Modulation current are set to open-loop operation. Output current range of I-DAC1 (or V-DAC3) for Modulation current and I-DAC2 for Bias current is set by R_DAC1_GAIN (or R_DAC3_GAIN) and R_DAC2_GAIN respectively. 3 LD power adjustment Set R_MOD_FF (Modulation current) and R_BIAS_FF (Bias current) so that designated LD power is available. 4-A PDGAIN adjustment Adjust PDMON-pin voltage when the designated LD power is output. (When to monitor Adjust PDMON-pin output voltage to be 1 [V] by R_PDGAIN. PDMON-pin voltage) Set R_APC_TRGT (APC target)"1 0000" (its center value), and after making APC setting (R_APC_FB_SET, R_APC_FF_SET, R_MOD_FBRT and R_BIAS_FBRT when both Bias and Modulation currents are used for APC_FB setting), jump to "Step 5" in this table. 4-B PDGAIN adjustment Set R_APC_TRGT (APC target)"1 0000" (its center value) and R_PDGAIN (When to monitor "00 0000" (23.5dB, Maximum gain), then make APC setting PDMON-pin voltage is (R_APC_FB_SET, R_APC_FF_SET, R_MOD_FBRT and R_BIAS_FBRT impossible) when both Bias and Modulation currents are used for APC_FB setting), Then APC_FB function is activated and LD power is lowered. Adjust R_PDGAIN so that LD power reaches a closest amount to the designated power level, and jump to "Step 5" in this table. 5 APC_FB Adjust DAC_APC setting value (R_APC_TRGT) so that LD optical power target adjustment reaches its designated power level. 6 Read-out of sensed Read out the LSI chip-surface temperature equivalent value (R_TEMP). temperature data 7 Calculation of In order to adjust the temperature characteristic of LD, vary temperature temperature and repeat "Steps 2 ~ 6" above when adjustment is made at 2 different characteristic temperature points or more and make the look-up table of I-DAC1 (or V-DAC3) and I-DAC2 with referring the measured data If the adjustment is executed at single temperature point, make the look-up table with the measured data and On-chip temperature sensor gain (1.5 /LSB [Typ.]). 8 Write the adjustment (1) Prepare the data to be written into EEPROM based on LD adjusting data. (2) Issue a command to make a transition into EEPROM Access Mode via data into EEPROM Digital I/F. (3) Write adjusting data into EEPROM. (4) Verify that correct data is written, by reading out the written data. 9 Transition to After writing data into EEPROM, issue a command to make a transition to Self-Operation Mode Self-Operation Mode via Digital I/F. Then the AK2572 automatically initiates its operation in accordance with the setting data retained in EEPROM.
< MS0290-E-01>
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ASAHI KASEI
[AK2572]
. EXTERNAL CIRCUIT EXAMPLE
Recommended External Circuit
LDD Voltage Output (VDAC3) Cvout Rvout Current Output (IDAC1) C13 C23 VDDBI VSSBI VDDMD VOUT3 IOUT1
LD Current Output (IDAC2) VDD=3.3V[typ] Monitor PD IOUT2 VSSBI Cpd Rpd
C14
C24
PDMON TEMPMON R11 BIAS EXTALM1 Extalm1 Extalm2/Mod_ctrl Open TEST4 WP TXFAULT TEST1 TEST2 TEST3 DVDD DVSS
BIASMON PDIN AVSS Current Output (BIASMON)
LDD
AK2572
AVDD TXDIS
C22
C12 R23
EXTALM2/MOD_CTRL
Tx_disable BURST Burst SCL Mod_def1 SDA
R21 * When Write Protect is Released : WP-pin is left Open or connected to DVDD (Set R_WP_CTRL='0') * When Write Protect is Established : WP-pin is left Open (Set R_WP_CTRL='1') or connected to DVSS C21 C11 Mod_def2 Tx_fault VSS=0V
R22
R11=12k1% fpd=1/(2*Rpd*Cpd)=5kHz10kHz Rvout=1k R21=R22=R23=4.7k10k C11=C12=C13=C14=0.1F Cvout=0.01F C21=C22=C23=C24=0.01F or 0.001F
Connection of Unused pins : BURST=VSS EXTALM1=VSS TXDIS=VSS EXTALM2/MOD_CTRL=VSS PDIN=VSS
< MS0290-E-01>
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ASAHI KASEI
[AK2572]
[A] Example of the connection to the LDD controlled by AK2572 voltage output for CW LD
LD IMODN
Current Control IMOD
LDD (CW)
Selector DATA FF DUTY _ADJ
CLK
DATAALM
AK2572
(E_MOD_TC) EXTALMx (E_EXTRA_TC) Monitor PD PDIN Cpd Rpd (E_BIAS_TC) I-DAC2 V-DAC3 I-DAC1
Voltage Control Vdac3 Rv Idac1 Vextra Ri Ci Ibias
Voltage Control Vmod Cv
BIASMON
(x0.012)
Idac2
[B] Example of the connection to the LDD controlled by AK2572 current output for CW LD
LD IMODN
Current Control IMOD
LDD (CW)
Selector DATA FF DUTY_ ADJ
CLK
DATAALM
AK2572
(E_EXTRA_TC) EXTALMx Monitor PD PDIN Cpd Rpd (E_BIAS_TC) I-DAC2 (E_MOD_TC) I-DAC1 V-DAC3
Voltage Control Vdac3 Rv Idac1 Vextra Cv
Current Control Imod
BIASMON
(x0.012)
Idac2
Ibias
< MS0290-E-01>
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ASAHI KASEI
[AK2572]
[C] Example of the connection to the LDD controlled by AK2572 current output for Burst transmission
LD IMODN IMOD IBIAS IBIASN
LDD (Burst)
DATA CLK FF Selector DUTY_ ADJ
BURST_ CONTROL Voltage Control V-DAC3 I-DAC1 Vdac3 Rv BURST_ CONTROL BURST Idac1 Ibiasmon (E_MOD_TC) Vextra Cv Current Control Imod Current Control Ibias
AK2572
(E_EXTRA_TC)
BIASMON
(x0.012)
(E_BIAS_TC)
I-DAC2
< MS0290-E-01>
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ASAHI KASEI
[AK2572]
IMPORTANT NOTICE l These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. l AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. l Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. l AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. l It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. -50-
< MS0290-E-01>
2004/8

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